Chapter-2: INSIDE AN INSTRUMENTATION AMPLIFIER 第二章：仪表放大器内部仪表放大器内部 1. A Simple Op Amp Subtractor Provides an In-Amp Function 简单运算放大器型简单运算放大器型减法器实现仪表放大器功能减法器实现仪表放大器功能 The simplest (but still very useful) method of implementing a differential gain block is shown in Figure 2-1. 差模增益模块最简单的实现方法如图 2-1。 If R1 = R3 and R2 = R4, then 如果 R1=R3，R2=R4，那么 VOUT=(VIN2−VIN1)R2 R1Although this circuit provides an in-amp function, amplifying differential signals while rejecting those that are common mode, it also has some limitations. 虽然该电路可以实现仪表放大器的功能，放大差模信号而抑制共模信号，但仍有其局限性。 First, the impedances of the inverting and non-inverting inputs are relatively low and unequal. In this example, the input impedance to VIN1 equals 100 kΩ, while the impedance of VIN2 is twice that, at 200 kΩ. Therefore, when voltage is applied to one input while grounding the other, different currents will flow depending on which input receives the applied voltage. (This unbalance in the sources’ resistances will degrade the circuit’s CMRR.). 首先，反相输入端、同相输入端的输入阻抗相对较低，而且不相等。本例，VIN1 端的输入阻抗为100KΩ，而 VIN2 输入端的阻抗为 200KΩ。因此，当一个输入端施加电压，另一输入端接地时，将产生差分电流，差分电流方向依赖于那个输入端施加信号、那个输入端接地。这种源电阻的不平衡会降低电路的共模抑制比。 Furthermore, this circuit requires a very close ratio match between resistor pairs R1/R2 and R3/R4; otherwise, the gain from each input would be different—directly affecting common-mode rejection. For example, at a gain of 1, with all resistors of equal value, a 0.1% mismatch in just one of the resistors will degrade the CMR to a level of 66 dB (1 part in 2000). Similarly, a source resistance imbalance of 100 will degrade CMR by 6 dB. 另外，该电路要求电阻对 R1/R2、R3/R4 具有严格的比值匹配，否则，两个输入端的信号会有增益差，直接影响共模抑制能力。例如，增益为 1 时、所有电阻等值选取的条件下，仅一个电阻 0.1%的失配度将使共模抑制比降低到66dB（两千分之一）。同样，源电阻失配 100 Ω，共模抑制比下降6dB。 In spite of these problems, this type of bare bones in-amp circuit, often called a difference amplifier or subtractor, is useful as a building block within higher performance in-amps. It is also very practical as a standalone functional circuit in video and other high speed uses, or in low frequency, high common-mode voltage (CMV) applications, where the input resistors divide down the input voltage as well as provide input protection for the amplifier. Some monolithic difference amplifiers such as Analog Devices’ AD629 employ a variation of the simple subtractor in their design. This allows the IC to handle common-mode input voltages higher than its own supply voltage. For example, when powered from a ±15 V supply, the AD629 can amplify signals with common-mode voltages as high as ±270 V. 暂且不考虑这些问题，这种不加任何修饰的仪表放大器“骨架”模型，经常叫做差动（差分）放大器，或减法器。作为较高性能的仪表放大器的内部构造模块非常有用，在视频及其它高速应用、低频应用、高共模电压应用中，作为功能电路也非常实用，输入电阻对输入电压的分压，构成放大器输入端的保护作用。一些单片差动放大器比如 ADI 公司的 AD629，在他们的设计中成为简单减法器的变形产品，使得他们的集成电路能够处理高于自身电源电压的共模信号。例如，采用 ±15V 电源电压时，AD629 能够处理混有高达±127 V共模电压的信号。 2. Improving the Simple Subtractor with Input Buffering 带有输入缓冲的改进型简单减法器 An obvious way to significantly improve performance is to add high input impedance buffer amplifiers ahead of the simple subtractor circuit, as shown in the 3-op amp instrumentation amplifier circuit of Figure 2-2. 一个明显能够显著改善性能的方法，就是在简单减法器电路前面增加高输入阻抗缓冲放大器。如图2-2 所示，为 3 个运算放大器构成的仪表放大器。 This circuit provides matched, high impedance inputs so that the impedances of the input sources will have a minimal effect on the circuit’s common-mode rejection. The use of a dual op amp for the 2-input buffer amplifiers is preferred because they will better track each other over temperature and save board space. Although the resistance values are different, this circuit has the same transfer function as the circuit of Figure 2-1. 该电路具有匹配、高阻的输入端，因而信号源对电路共模抑制能力的影响降至最低。首选推荐方案，采用双运算放大器构成两个输入缓冲放大器，因为温度变化时二者（处于同一封装内）能够相互跟踪；采用双运算放大器还可以节省电路空间。尽管电阻值不同，该电路与图 2-1 电路具有相同的传输函数。 Figure 2-3 shows further improvement: Now the input buffers are operating with gain, which provides a circuit with more flexibility. If the value of R5 = R8 and R6 = R7 and, as before, R1 = R3 and R2 = R4, then 进一步改进如图 2-3 所示：此时的输入缓冲级具有了增益，使电路更加灵活。如果电阻值满足 R5 = R8 ，R6 = R7，R1 = R3 R2 = R4，那么 VOUT=(VIN2−VIN!)(1+R5R2)() R6R1While the circuit of Figure 2-3 does increase the gain (of A1 and A2) equally for differential signals, it also increases the gain for common-mode signals. 然而，图 2-3 电路在同等程度提高缓冲放大器 A1、A2 的增益的同时，也提高了共模信号的增益。 3. The 3-Op Amp In-Amp 三运算放大器型仪表放大器 The circuit of Figure 2-4 provides further refinement and has become the most popular configuration for instrumentation amplifier design. The classic 3-op amp in-amp circuit is a clever modification of the buffered subtractor circuit of Figure 2-3. As with the previous circuit, op amps A1 and A2 of Figure 2-4 buffer the input voltage. However, in this configuration, a single gain resistor, RG, is connected between the summing junctions of the two input buffers, replacing R6 and R7. The full differential input voltage will now appear across RG (because the voltage at the summing junction of each amplifier is equal to the voltage applied to its positive input). Since the amplified input voltage (at the outputs of A1 and A2) appears differentially across the three resistors, R5, RG, and R6, the differential gain may be varied by just changing RG. 图 2-4 电路为进一步改良的电路，已经具备了仪表放大器设计的最普遍的配置形式。经典的 3 运算放大器型仪表放大器，是对图 2-3 带有输入缓冲放大级的减法器电路的又一次绝妙修改。与前述电路一样，图 2-4 电路中的运算放大器 A1、A2 同样对输入电压进行缓冲。但是，本电路中，只有一个电阻 RG 连接在两个输入缓冲器的公共节点之间，以此代替原来的 R6、R7。全部差模输入电压出现在RG两端（因为每个缓冲放大器公共节点上的电压等于施加在同相输入端的电压）。由于被放大了的输入电压（A1、A2输出端）以差分形式出现在三个电阻R5、RG、R6两端，因此可通过调节 RG 来调节差模增益。 There is another advantage of this connection: Once the subtractor circuit has been set up with its ratio-matched resistors, no further resistor matching is required when changing gains. If the value of R5 = R6, R1 = R3, and R2 = R4, then 这样的连接还有另一个优点：一旦后面的减法器电路搭建完成，且所用电阻满足比值匹配条件，在改变增益过程中，无需再次进行电阻匹配。如果满足R5 = R6、R1 = R3、 R2 = R4，那么 VOUT=(VIN2−VIN!)(1+2R5R2)() RGR1Since the voltage across RG equals VIN, the current through RG will equal (VIN/RG). Amplifiers A1 and A2, therefore, will operate with gain and amplify the input signal. Note, however, that if a common-mode voltage is applied to the amplifier inputs, the voltages on each side of RG will be equal, and no current will flow through this resistor. Since no current flows through RG (nor, therefore, through R5 and R6), amplifiers A1 and A2 will operate as unity-gain followers. Therefore, common mode signals will be passed through the input buffers at unity gain, but differential voltages will be amplified by the factor (1 + (2 RF/RG)). 因为电阻 RG 两端的电压等于 VIN，流过 RG 的电流等于VIN / RG，因此放大器 A1、A2 具有增益，可对输入信号放大。请注意，如果共模电压施加在放大器输入端，该电压在电阻 RG 的两端相等，不会在 RG 上产生电流，没有电流流过 RG，也就不会有电流流过 R5、R6，因此放大器 A1、A2为单位增益的电压跟随器。因此，共模信号以单位增益通过输入缓冲级，但差模信号以增益（1+2RF/RG）被放大。 In theory, this means that the user may take as much gain in the front end as desired (as determined by RG) without increasing the common-mode gain and error. That is, the differential signal will be increased by gain, but the common-mode error will not, so the ratio (Gain (VDIFF)/(VERROR CM)) will increase. Thus, CMRR will theoretically increase in direct proportion to gain—a very useful property. 从原理上，意味着用户可以在前端选取较大的增益（由电阻 RG 确定）而不会增加共模增益及误差。也就是说，差模信号以指定的增益被放大，共模信号不被放大，因此差模信号增益、共模信号增益之比值可任意增大，即理论上，共模抑制比随增益增大而正比例增大，这是一个非常有用的特性。 Finally, because of the symmetry of this configuration, common-mode errors in the input amplifiers, if they track, tend to be canceled out by the output stage subtractor. This includes such errors as common-mode rejection vs. frequency. These features explain the popularity of this configuration. 最终，由于这种结构的对称性，如果输入级的共模误差相互跟踪，势必被输出减法器消减掉，其中也包含共模抑制比随频率变化而产生的误差。这些特征就是这种结构普遍流行的合理解释。 4. 3-Op Amp In-Amp Design Considerations 3 运算放大器型仪表放大器设计需要考虑的因素 Two alternatives are available for constructing 3-op amp instrumentation amplifiers: using FET or bipolar input operational amplifiers. FET input op amps have very low bias currents and are generally well-suited for use with very high (>106Ω) source impedances. FET amplifiers usually have lower CMR, higher offset voltage, and higher offset drift than bipolar amplifiers. They also may provide a higher slew rate for a given amount of power. 构建 3 运算放大器型仪表放大器，有两中可选方案：应用场效应管，或双极性晶体管输入的运算放大器。场效应管输入的运算放大器具有偏置电流低的特点，因而适合信源阻抗极高（大于106Ω）的应用中。与双极性晶体管放大器相比，场效应管放大器通常共模抑制比较低、失调电压较高、失调电压漂移较高。但在给定电源电压条件下，场效应管放大器电压摆率较高。 The sense and reference terminals (Figure 2-4) permit the user to change A3’s feedback and ground connections. The sense pin may be externally driven for servo applications and others for which the gain of A3 needs to be varied. Likewise, the reference terminal allows an external offset voltage to be applied to A3. For normal operation, the sense and output terminals are tied together, as are reference and ground. 图 2-4 电路中的灵敏度端子（sense）、参考端子（reference）允许用户改变放大器 A3 的反馈和接地。在伺服应用或其它应用中，如果要求 A3 增益可变，Sense 引脚可由外电路驱动；同样地，reference 引脚允许放大器 A3 施加外部偏差电压。通常情况。Sense 引脚与输出引脚连接在一起，reference 引脚与地接在一起。 Amplifiers with bipolar input stages tend to achieve both higher CMR and lower input offset voltage drift than FET input amplifiers. Super-beta bipolar input stages combine many of the benefits of FET and bipolar processes, with even lower IB drift than FET devices. 与场效应管输入放大器相比，双极性晶体管输入放大器，倾向于达到较高的共模抑制比、较低的输入失调电压漂移。应用超β管的双极性晶体管输入级的放大器，结合了场效应晶体管、双极性晶体管的优点，输入偏置电流甚至比场效应管还要低。 A common (but frequently overlooked) issue for the unwary designer using a 3-op amp in-amp design is the reduction of common-mode voltage range that occurs when the in-amp is operating at high gain. Figure 2-5 is a schematic of a 3-op amp in-amp operating at a gain of 1000. 对于粗心的设计者，应用 3 运算放大结构的仪表放大器，存在一个普遍的同时也是经常被忽视的问题，仪表放大器工作在高增益情况下，共模电压范围降低。图 2-5 为一个增益为 1000 的 3 运算放大器型仪表放大器。 In this example, the input amplifiers, A1 and A2, are operating at a gain of 1000, while the output amplifier is providing unity gain. This means that the voltage at the output of each input amplifier will equal one-half the peak-to-peak input voltage×1000, plus any common-mode voltage that is present on the inputs (the common-mode voltage will pass through at unity gain regardless of the differential gain). Therefore, if a 10 mV differential signal is applied to the amplifier inputs, amplifier A1’s output will equal +5 V, plus the common-mode voltage, and A2’s output will be –5 V, plus the common-mode voltage. If the amplifiers are operating from 15 V supplies, they will usually have 7 V or so of headroom left, thus permitting an 8V common-mode voltage—but not the full 12 V of CMV, which, typically, would be available at unity gain (for a 10 mV input). Higher gains or lower supply voltages will further reduce the common-mode voltage range. 本例，输入放大器 A1、A2 增益为1000，输出放大器为单位增益。就是说，每个输入放大器输出端的电压等于 1000 倍的输入电压峰峰值的一半，再加上输入端的共模电压（共模电压不同于差模电压，增益为单位增益）。因此，如果 10mV 的差模信号施加于放大器输入端，A1 输出电压等于+5V 再加上共模电压；A2 输出电压为 -5V 再加上共模电压。如果放大器电源电压为 15V，一般要预留7V左右的净空电压，那么只允许 8V 共模电压，并非 12V 的满度共模电压。12V，是 10mV 输入、单位增益条件下，典型的满度共模电压。增益提高、电源电压降低势必会减小共模电压范围。 5. The Basic 2-Op Amp Instrumentation Amplifier 基本的2运算放大器型仪表放大器 Figure 2-6 is a schematic of a typical 2-op amp in-amp circuit. It has the obvious advantage of requiring only two, rather than three, operational amplifiers and providing savings in cost and power consumption. However, the nonsymmetrical topology of the 2-op amp in-amp circuit can lead to several disadvantages, most notably lower ac CMRR compared to the 3-op amp design, limiting the circuit’s usefulness. 图 2-6 为典型的 2 运算放大器型仪表放大器电路，它的优势是显而易见的：仅用两个而不是三个运算放大器，节省运算放大器和电源损耗。但是，2 运算放大器型的非对称性拓补结构也带来一些不足，与 3 运算放大器相比，共模抑制比显著降低，因而应用受限。 The transfer function of this circuit is 该电路传输函数为 VOUT=(VIN2−VIN1)(1+R1=R3R2=R4R4)R3 Input resistance is high and balanced, thus permitting the signal source to have an-unbalanced output impedance. The circuit’s input bias currents are set by the input current requirements of the noninverting input of the two op amps, which typically are very low. 输入阻抗高且平衡，因而允许信号源为非平衡输出阻抗。输入偏置电流决定于两个运算放大器同相输入端的电流要求，偏置电流一般非常低。 Disadvantages of this circuit include the inability to operate at unity gain, a decreased common-mode voltage range as circuit gain is lowered, and poor ac common-mode rejection. The poor CMR is due to the unequal phase shift occurring in the two inputs, VIN1 and VIN2. That is, the signal must travel through amplifier A1 before it is subtracted from VIN2 by amplifier A2. Thus, the voltage at the output of A1 is slightly delayed or phase-shifted with respect to VIN1. 该电路的缺点：无法单位增益工作；低增益时共模电压范围变小；交流共模抑制不足。交流共模抑制比降低的原因是两个输入端 VIN1、VIN2 的信号相移不相等，信号要经过运算放大器 A1，才能因此放大器 A1 输出信号相对于VIN1的信号具有轻微延时与 VIN2 的信号在放大器 A2 实现相减，或相移。 Minimum circuit gains of 5 are commonly used with the 2-op amp in-amp circuit because this permits an adequate dc common-mode input range, as well as sufficient bandwidth for most applications. The use of rail-to-rail (single-supply) amplifiers will provide a common-mode voltage range that extends down to –VS (or ground in single-supply operation), plus true rail-to-rail output voltage range (i.e., an output swing from +VS to –VS). 这种 2 运算放大器型仪表放大器，最低增益一般用在5倍，这样可以有充足的共模电压输入范围，同时满足多数应用中的有效带宽。应用轨至轨放大器时，共模电压输入范围可扩展到-Vs（单电源工作时为地），加上真正的轨至轨输出电压范围，即输出摆幅为 –Vs ~ +Vs 。 Table 2-1 shows amplifier gain vs. circuit gain for the circuit of Figure 2-6 and gives practical 1% resistor values for several common circuit gains. 表 2-1 为图 2-6 电路放大器增益与电路增益的关系，并给出几种常用增益对应的实际电阻值（1%精度电阻）。 6. 2-Op Amp In-Amps—Common-Mode Design Considerations for Single-Supply Operation 2 运算放大器型仪表放大器 ------ 单电源工作时，单电源工作时，共模设计的考虑因素 When the 2-op amp in-amp circuit of Figure 2-7 is examined from the reference input, it is apparent that it is simply a cascade of two inverters. Assuming that the voltage at both of the signal inputs, VIN1 and VIN2, is 0, the output of A1 will equal 图 2-7 电路，从参考输入端看起，就是两级反相器的一个简单级联。假定两个信号输入端 VIN1、VIN2 的电压都为零，那么，A1 的输出电压为 Vo1=−R2VREF R1A positive voltage applied to VREF will tend to drive the output voltage of A1 negative, which is clearly not possible if the amplifier is operating from a single power supply voltage (+VS and 0 V). 一个正电压施加到 VREF 端，就有迫使放大器输出负电压的趋势，但是在单电源工作条件（0V ~ Vs）下，显然不可能输出负电压。 The gain from the output of amplifier A1 to the circuit’s output, VOUT, at A2, is equal to 从放大器 A1 的输出到电路输出 VOUT，放大器 A2 的增益为 VOUT=−R4VRo1 R3The gain from VREF to VOUT is the product of these two gains and equals 从 VREF 到 VOUT 的增益，就是以上两个增益的乘积，即： VOUT=R2R4VREF R1R3In this case, R1 = R4 and R2 = R3. Therefore, the reference gain is +1, as expected. Note that this is the result of two inversions, in contrast to the non-inverting signal path of the reference input in a typical 3-op amp in-amp circuit. 本例，R1 = R4，R2 = R3，因此参考信号的增益为 1，这正如我们所期望的。注意，与典型的 3 运算放大器型仪表放大器没有反相通路的情形不同，本例增益为 1 是经过两次反相的结果。 Just as with the 3-op amp in-amp, the common-mode voltage range of the 2-op amp in-amp can be limited by single-supply operation and by the choice of reference voltage. 如同 3 运算放大器型仪表放大器，2 运算放大器型仪表放大器的共模电压范围也受限于单电源供电和参考电压的选择。 Figure 2-8 is a schematic of a 2-op amp in-amp operating from a single 5 V power supply. The reference input is tied to VS/2, which in this case is 2.5 V. The output voltage should ideally be 2.5 V for a differential input voltage of 0 V and for any common-mode voltage within the power supply voltage range (0 V to 5 V). 图 2-8 为一个单电源 5V 电压供电的 2 运算放大器型仪表放大器电路，参考电压为Vs / 2，本例即2.5V。差模输入电压为 0，共模输入电压为 0 ~ 5 V 范围内的任意值时，输出电压值在理想情况下为 2.5V。 As the common-mode voltage is increased from 2.5 V toward 5 V, the output voltage of A1 (VO1) will equal 共模电压从 2.5V 增长到 5V，放大器 A1 输出电压VO1为 Vo1=VCM+R2(VCM−VREF) R1In this case, VREF = 2.5 V and R2/R1 = 1/4. The output voltage of A1 will reach 5 V when VCM = 4.5 V. Further increases in common-mode voltage obviously cannot be rejected. In practice, the input voltage range limitations of amplifiers A1 and A2 may limit the in-amp’s common mode voltage range to less than 4.5 V. 本例，VREF = 2.5V，R2/R1 = 1/4。当 VCM = 4.5 V 时，放大器 A1 输出电压达到 5V。显然，（因为继续增长的共模电压已经无法再共模电压继续增长，已不能在仪表放大器的输出端被抑制掉现于放大器 A1 的输出端，也就无法被放大器 A2 抵消掉------译者注）。本质原因是，放大器 A1、A2 的输入电压范围，限定了仪表放大器共模电压范围低于 4.5V。 Similarly, as the common-mode voltage is reduced from 2.5 V toward 0 V, the output voltage of A1 will hit zero for a VCM of 0.5 V. Clearly, the output of A1 cannot go more negative than the negative supply line (assuming no charge pump), which, for a single-supply connection, equals 0 V. This negative or zero-in common-mode range limitation can be overcome by proper design of the in-amp’s internal level shifting, as in the AD627 monolithic 2-op amp instrumentation amplifier. However, even with good design, some positive common-mode voltage range will be traded off to achieve operation at zero common-mode voltage. 类似地，共模电压 VCM 从 2.5V 下降到 0V 的过程中，在 VCM = 0.5 V 时，放大器 A1 的输出电压过零。显然，放大器 A1 的输出电压不会更负（假定内部不存在电荷泵的情况下），在单电源工作条件下，放大器输出最低就是 0V。共模电压范围的这个 0V 或负端电压的，可以通过仪表放大器内部电平移动电路的正确设计来克服，比如AD627 单片 2 运算放大器型仪表放大器。但是，即使采用更好的设计，共模电压范围的正（上）端，也要权衡考虑，使放大器可以零共模电压工作。 Another, and perhaps more serious, limitation of the standard 2-amplifier instrumentation amplifier circuit compared to 3-amplifier designs, is the intrinsic difficulty of achieving high ac common-mode rejection. This limitation stems from the inherent imbalance in the common-mode signal path of the 2-amplifier circuit. 与 3 运算放大器型仪表放大器相比，标准 2 运算放大器型仪表放大器电路的还有一个、也许是更严重的应用。2 运算放大器型仪表放大器存在一个固有的困难，交流高共模抑制能力的提高。这个困难起源于共模信号通路固有的不平衡。 Assume that a sinusoidal common-mode voltage, VCM, at a frequency, FCM, is applied (common mode) to inputs VIN1 and VIN2 (Figure 2-8). Ideally, the amplitude of the resulting ac output voltage (the common-mode error) should be 0 V, independent of frequency, FCM, at least over the range of normal ac power line (mains) frequencies: 50 Hz to 400 Hz. Power lines tend to be the source of much common-mode interference. 假定正弦共模电压 VCM，频率 fCM 的信号，施加于输入端 VIN1、VIN2（图2-8）。理想情况下，交流输出电压（共模误差）应该为0V，与频率 fCM 无关，至少在通常的电力频率范围 50 Hz ~ 400 HZ 范围内应该是这样。电力线往往是众多共模干扰的源。 If the ac common-mode error is zero, amplifier A2 and gain network R3, R4 must see zero instantaneous difference between the common-mode voltage, applied directly to VIN2, and the version of the common-mode voltage that is amplified by A1 and its associated gain network R1, R2. Any dc common-mode error (assuming negligible error from the amplifier’s own CMRR) can be nulled by trimming the ratios of R1, R2, R3, and R4 to achieve the balance： 如果共模误差为零，放大器 A2 和增益网络 R3、R4 “看到”的是：直接施加在 VIN2 共模电压、经过放大器 A1 及其增益网络 R1、R2 的共模电压，二者瞬时差值为零。如果忽略放大器自身的共模误差，一切直流误差可通过电阻 R1、R2、R3、R4 的比率校准而归零，从而达到平衡： R1≡R4 同时 R2≡R3 However, any phase shift (delay) introduced by amplifier A1 will cause the phase of VO1 to slightly lag behind the phase of the directly applied common-mode voltage of VIN2. This difference in phase will result in an instantaneous (vector) difference in VO1 and VIN2, even if the amplitudes of both voltages are at their ideal levels. This will cause a frequency-dependent common-mode error voltage at the circuit’s output, VOUT. Further, this ac common-mode error will increase linearly with common-mode frequency because the phase shift through A1 (assuming a single-pole roll-off) will increase directly with frequency. In fact, for frequencies less than 1/10th the closed-loop bandwidth (fT1) of A1, the common-mode error (referred to the input of the in-amp) can be approximated by 但是，放大器 A1 引入的相移（或者说时延）使得 Vo1 的相位比直接施加在 VIN2 的共模电压的相位稍微滞后。这个相差造成 Vo1 与 VIN2 之间的瞬时差，即使这两个信号的电压幅度为理想电平，在电路输出端 VOUT 产生一个频率相关的共模误差电压。进而，这个交流共模误差随频率 fCM线性增加，因为通过放大器 A1 的相移随频率正比增长（假定为单极点滚降）。事实上，频率低于放大器 A1 的闭环带宽（fT1）的1 / 10 的条件下，共模误差（相对于仪表放大器输入）可近似表示为： CMerror(%)=VE/Gf×100%=CM×100% VCMfT1where VE is the common-mode error voltage at VOUT, and G is the differential gain—in this case, 5. 式中，VE 为仪表放大器输出端 VOUT 的共模误差电压；G 为差模增益，本例等于 5。 For example, if A1 has a closed-loop bandwidth of 100 kHz (a typical value for a micropower op amp), when operating at the gain set by R1 and R2, and the common-mode frequency is 100 Hz, then 举例说明。如果放大器 A1 的闭环带宽为 100 KHz （微功耗运算放大器典型值），当工作在 R1、R2 设定的增益时，并且共模信号频率为 100Hz，那么 CMerror(%)=100×100%=0.1% 100KA common-mode error of 0.1% is equivalent to 60 dB of common-mode rejection. So, in this example, even if this circuit were trimmed to achieve 100 dB CMR at dc, this would be valid only for frequencies less than 1 Hz. At 100 Hz, the CMR could never be better than 60 dB. 0.1% 的共模误差相当于 60dB 的共模抑制比。本例中，电路即使通过校准达到 100dB 的直流共模抑制比，也仅仅在频率低于1Hz 条件下有效。在100Hz，共模抑制比不会优于 60dB。 The AD627 monolithic in-amp embodies an advanced version of the 2-op amp instrumentation amplifier circuit that overcomes these ac common-mode rejection limitations. As illustrated in Figure 2-9, the AD627 maintains over 80 dB of CMR out to 8 kHz (gain of 1000), even though the bandwidth of amplifiers A1 and A2 is only 150 kHz. AD627 单片仪表放大器包含一个高版本的 2 运算放大器电路，突破了交流共模抑制比的。如图 2-9，AD627 在 8KHz 以上，还能保持高于 80dB 的共模抑制比（增益为1000），即使放大器A1、A2 的带宽只有 150KHz。 The four resistors used in the subtractor are normally internal to the IC and are usually of very high resistance. High common-mode voltage difference amps (diff amps) typically use input resistors selected to provide voltage attenuation. Therefore, both the differential signal voltage and the common-mode voltage are attenuated, the common mode is rejected, and then the signal voltage is amplified. 减法器所用 4 个电阻通常为芯片内置电阻，并且阻值非常大。高共模电压的差动放大器，输入电阻的选择，一般使放大器实际为一个衰减器。因此，差模信号、共模信号均被衰减，抑制共模信号，然后再放大差模信号。
