Image size reduction circuit for reducing ordinary

专利名称：Image size reduction circuit for reducing

ordinary-sized image into smaller area

发明人：Sawada, Akira c/o NEC Corporation申请号：EP89120137.8申请日：19891030公开号：EP0371270A3公开日：19900919

专利附图：

摘要：An image squeezing circuit produces an output image carrying signal (S2) forreproducing an small-sized image 1/ times larger than an ordinary-sized image (where isan integer not less than two), and an input image carrying signal (S1) is separated for

producing an analog chrominance subcarrier signal (D1), an analog luminance signal (Y1)and a color subcarrier signal (F1), wherein the analog luminance signal is sampled with asampling signal (F5) / times larger in frequency than the color subcarrier signal (where isan integer not less than three) for producing a decimated digital luminance signal(Y3) butthe analog chrominance subcarrier signal is sampled with another sampling signal (F4)times larger in frequency than the color subcarrier signal in every pulse intervals of thecolor subcarrier signal for producing a decimated digital chrominance signal (D3), thedecimated digital luminance signal and the decimated digital chrominance signal beingsupplied to respective digital-to-analog converting circuits (215 and 315) in response to ahigh frequency pulse signal (F2) times larger in frequency than the color subcarrier signalfor producing the output image carrying signal.

申请人：NEC CORPORATION

地址：7-1, Shiba 5-chome Minato-ku Tokyo JP

国籍：JP

代理机构：Glawe, Delfs, Moll & Partner

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