Information processing device

专利名称：Information processing device发明人：Tetsuya Yamada,Naohiko Irie,Takahiro

Irita,Masayuki Kabasawa

申请号：US10883758申请日：20040706

公开号：US20050027965A1公开日：20050203

专利附图：

摘要：A hardware accelerator is used to execute a floating-point byte-code in aninformation processing device. For a floating-point byte-code, a byte-code acceleratorBCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the

data is transferred to the FPU register from a general-purpose register, and then an FPUoperation is performed. For data, such as a denormalized number, that cannot beprocessed by the FPU, in order to call a floating-point math library of software, theprocessing of the BCA is completed and the processing moves to processing by software.In order to realize this, data on a data transfer bus from the CPU to the FPU is snoopedby the hardware accelerator, and a cancel request is signaled to the CPU to inhibitexecution of the FPU operation when 4corresponding data is detected in a data checkingpart.

申请人：Tetsuya Yamada,Naohiko Irie,Takahiro Irita,Masayuki Kabasawa

地址：Tokyo JP,Tokyo JP,Tokyo JP,Yokohama JP

国籍：JP,JP,JP,JP

更多信息请下载全文后查看