Integrated circuit and associated design method us

专利名称：Integrated circuit and associated design

method using spare gate islands

发明人：Craig Bingert,Christopher D. Gorsuch,Oscar

G. Mercado,Anthony K. Myers,John A.Schadt,Brian W. Yeager

申请号：US10135325申请日：20020430公开号：US06600341B2公开日：20030729

专利附图：

摘要：An integrated circuit includes standard cells interspersed with islands of spare

gates. The spare gates are arranged in multiple groups of spare gates, with each groupof spare gates within a corresponding designated spare gate area of a standard cellportion of the integrated circuit. At least a given one of the groups of spare gates isarranged between first and second rows of the standard cells and includes one or morerows of spare gates, with each row of spare gates including multiple base transistorstructures arranged adjacent to one another along longitudinal dimensions of thestructures. The standard cells and spare gates are preferably placed in accordance with aplacement operation of an automated place and route process of a standard cellcomputer-aided design (CAD) tool. The spare gates may be implemented using a basetransistor structure compatible with the standard cell CAD tool. The spare gate islandsmay be distributed throughout the standard cell portion of the integrated circuit in asubstantially uniform manner, for example, in accordance with a predetermined

geometric pattern. The spare gates may be converted to active gates in conjunction withthe automated place and route process using only conductors in one or more metallayers of the integrated circuit.

申请人：LATTICE SEMICONDUCTOR CORP.

更多信息请下载全文后查看