IC41LV16100AS-50K资料

IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

Document Title1M x 16 bit Dynamic RAM with EDO Page Mode

Revision HistoryRevision No

0A

History

Initial Draft

Draft DateRemark

September 28,2001

Integrated Circuit Solution Inc.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

1M x 16 (16-MBIT) DYNAMIC RAMWITH EDO PAGE MODE

FEATURES

••••••

Extended Data-Out (EDO) Page Mode access cycleTTL compatible inputs and outputs; tristate I/ORefresh Interval: 1,024 cycles /16 msRefresh Mode:

RAS-Only, CAS-before-RAS (CBR), and HiddenJEDEC standard pinoutSingle power supply:

5V ± 10% (IC41C16100A(S)) 3.3V ± 10% (IC41LV16100A(S))

Byte Write and Byte Read operation via two CASSelf Refresh 1024 cycles for S version

DESCRIPTION

The ICSI IC41C16100A(S) and IC41LV16100A(S) are 1,048,

576 x 16-bit high-performance CMOS Dynamic RandomAccess Memories. These devices offer an accelerated cycleaccess called EDO Page Mode. EDO Page Mode allows 1,024random accesses within a single row with access cycle time asshort as 20 ns per 16-bit word. The Byte Write control, of upperand lower byte, makes the 16100 series ideal for use in16-, 32-bit wide data bus systems.

These features make the IC41C16100A(S) and IC41LV16100A(S) ideally suited for high-bandwidth graphics, digital signalprocessing, high-performance computing systems, andperipheral applications.

The IC41C16100A(S) and IC41LV16100A(S) are packaged in a42-pin 400mil SOJ and 400mil 50- (44-) pin TSOP-2.

••

KEY TIMING PARAMETERS

Parameter

Max. RAS Access Time (tRAC)Max. CAS Access Time (tCAC)

Max. Column Address Access Time (tAA)Min. EDO Page Mode Cycle Time (tPC)Min. Read/Write Cycle Time (tRC)

-505013252084

-6060153025104

Unitnsnsnsnsns

PIN CONFIGURATIONS

50(44)-Pin TSOP-2

VCCI/O0I/O1I/O2I/O3VCCI/O4I/O5I/O6I/O7NC NCNCWERASNCNCA0A1A2A3VCC15161718192021222324253635343332313029282726NCLCASUCASOEA9A8A7A6A5A4GND12345671011504948474443424140GNDI/O15I/O14I/O13I/O12GNDI/O11I/O10I/O9I/O8NC42-Pin SOJ

VCCI/O0I/O1I/O2I/O3VCCI/O4I/O5I/O6I/O7NCNCWERASNCNCA0A1A2A3VCC1234567101112131415161718192021424140393837363534333231302928272625242322GNDI/O15I/O14I/O13I/O12GNDI/O11I/O10I/O9I/O8NCLCASUCASOEA9A8A7A6A5A4GNDPIN DESCRIPTIONS

A0-A9I/O0-15WEOERASUCASLCASVccGNDNC

Address InputsData Inputs/OutputsWrite EnableOutput EnableRow Address Strobe

Upper Column Address StrobeLower Column Address StrobePowerGroundNo Connection

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errorswhich may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

FUNCTIONAL BLOCK DIAGRAMOEWELCASUCASCAS CLOCKGENERATORWE CONTROLLOGICSOE CONTROLLOGICCASWEOERASRAS CLOCKGENERATORDATA I/O BUSCOLUMN DECODERSSENSE AMPLIFIERSREFRESH COUNTERDATA I/O BUFFERSROW DECODERRASI/O0-I/O15MEMORY ARRAY1,048,576 x 16A0-A9ADDRESSBUFFERSIntegrated Circuit Solution Inc.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

TRUTH TABLE

FunctionStandbyRead: WordRead: Lower ByteRead: Upper ByteWrite: Word (Early Write)Write: Lower Byte (Early Write)Write: Upper Byte (Early Write)Read-Write(1,2)EDO Page-Mode Read(2)RASHLLLLLLLCASUCASHHLLLHHLLHLH→LH→LL→HH→LH→LH→LH→LLLHLLLHLLH→LH→LL→HH→LH→LH→LH→LLLHLWEXHHHLLLH→LHHHLLH→LH→LHLXXOEXLLLXXXL→HLLLXXL→HL→HLXXXAddress tR/tCXROW/COLROW/COLROW/COLROW/COLROW/COLROW/COLROW/COLROW/COLNA/COLNA/NAROW/COLNA/COLROW/COLNA/COLROW/COLROW/COLROW/NAXI/OHigh-ZDOUTLower Byte, DOUTUpper Byte, High-ZLower Byte, High-ZUpper Byte, DOUTDINLower Byte, DINUpper Byte, High-ZLower Byte, High-ZUpper Byte, DINDOUT, DINDOUTDOUTDOUTDINDINDOUT, DINDOUT, DINDOUTDINHigh-ZHigh-ZEDO Page-Mode Write(1)EDO Page-Mode(1,2)Read-WriteHidden RefreshRAS-Only RefreshCBR Refresh(4)L1st Cycle:L2nd Cycle:LAny Cycle:L1st Cycle:L2nd Cycle:L1st Cycle:L2nd Cycle:LRead(2)L→H→LWrite(1,3)L→H→LLH→LNotes:

1.These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).2.These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).3.EARLY WRITE only.

4.At least one of the two CAS signals must be active (LCAS or UCAS).

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

Functional Description

The IC41C16100A(S) and IC41LV16100A(S) is a CMOSDRAM optimized for high-speed bandwidth, low powerapplications. During READ or WRITE cycles, each bit isuniquely addressed through the 16 address bits. Theseare entered ten bits (A0-A9) at a time. The row address islatched by the Row Address Strobe (RAS). The columnaddress is latched by the Column Address Strobe (CAS).RAS is used to latch the first ten bits and CAS is used thelatter ten bits.

The IC41C16100A(S) and IC41LV16100A(S) has two CAScontrols, LCAS and UCAS. The LCAS and UCAS inputsinternally generates a CAS signal functioning in an iden-tical manner to the single CAS input on the other 1M x 16DRAMs. The key difference is that each CAS controls itscorresponding I/O tristate logic (in conjunction with OEand WE and RAS). LCAS controls I/O0 through I/O7 andUCAS controls I/O8 through I/O15.

The IC41C16100A(S) and IC41LV16100A(S) CAS func-tion is determined by the first CAS (LCAS or UCAS)transitioning LOW and the last transitioning back HIGH.The two CAS controls give the IC41C16100A(S) andIS41LV16100A(S) both BYTE READ and BYTE WRITEcycle capabilities.

cycle, an internal 10-bit counter provides the row ad-dresses and the external address inputs are ignored.CAS-before-RAS is a refresh-only mode and no dataaccess or device selection is allowed. Thus, the outputremains in the High-Z state during the cycle.

Self Refresh Cycle

The Self Refresh allows the user a dynamic refresh, dataretention mode at the extended refresh period of 128 ms.i.e., 125 µs per row when using distributed CBR refreshes.The feature also allows the user the choice of a fully static,low power data retention mode. The optional Self Refreshfeature is initiated by performing a CBR Refresh cycle andholding RAS LOW for the specified tRASS.

The Self Refresh mode is terminated by driving RAS HIGHfor a minimum time of tRPS. This delay allows for thecompletion of any internal refresh cycles that may be inprocess at the time of the RAS LOW-to-HIGH transition.If the DRAM controller uses a distributed refresh sequence,a burst refresh is not required upon exiting Self Refresh.However, if the DRAM controller utilizes a RAS-only orburst refresh sequence, all 1,024 rows must be refreshedwithin the average internal refresh rate, prior to the re-sumption of normal operation.

Memory Cycle

A memory cycle is initiated by bring RAS LOW and it isterminated by returning both RAS and CAS HIGH. Toensures proper device operation and data integrity anymemory cycle, once initiated, must not be ended oraborted before the minimum tRAS time has expired. A newcycle must not be initiated until the minimum prechargetime tRP, tCP has elapsed.

Extended Data Out Page Mode

EDO page mode operation permits all 1,024 columnswithin a selected row to be randomly accessed at a highdata rate.

In EDO page mode read cycle, the data-out is held to thenext CAS cycle’s falling edge, instead of the rising edge.For this reason, the valid data output time in EDO pagemode is extended compared with the fast page mode. Inthe fast page mode, the valid data output time becomesshorter as the CAS cycle time becomes shorter. Therefore,in EDO page mode, the timing margin in read cycle islarger than that of the fast page mode even if the CAScycle time becomes shorter.

In EDO page mode, due to the extended data function, theCAS cycle time can be shorter than in the fast page modeif the timing margin is the same.

The EDO page mode allows both read and write opera-tions during one RAS cycle, but the performance isequivalent to that of the fast page mode in that case.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE,whichever occurs last, while holding WE HIGH. Thecolumn address must be held for a minimum time specifiedby tAR. Data Out becomes valid only when tRAC, tAA, tCACand tOEA are all satisfied. As a result, the access time isdependent on the timing relationships between theseparameters.

Write Cycle

A write cycle is initiated by the falling edge of CAS andWE, whichever occurs last. The input data must be validat or before the falling edge of CAS or WE, whicheveroccurs first.

Power-On

After application of the VCC supply, an initial pause of200 µs is required followed by a minimum of eight initial-ization cycles (any combination of cycles containing aRAS signal).

During power-on, it is recommended that RAS track withVCC or be held at a valid VIH to avoid current surges.

Refresh Cycle

To retain data, 1,024 refresh cycles are required in each16 ms period. There are two ways to refresh the memory.1.By clocking each of the 1,024 row addresses (A0through A9) with RAS at least once every 16 ms. Anyread, write, read-modify-write or RAS-only cycle re-freshes the addressed row.

2.Using a CAS-before-RAS refresh cycle. CAS-before-RAS refresh is activated by the falling edge of RAS,while holding CAS LOW. In CAS-before-RAS refreshIntegrated Circuit Solution Inc.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

ABSOLUTE MAXIMUM RATINGS(1)

SymbolVTVCCIOUTPDTATSTG

Parameters

Voltage on Any Pin Relative to GNDSupply Voltage

Output CurrentPower Dissipation

Commercial Operation TemperatureStorage Temperature

5V3.3V5V3.3V

Rating–1.0 to +7.0–0.5 to +4.6–1.0 to +7.0–0.5 to +4.6

5010 to +70–55 to +125

UnitVVmAW°C°C

Note:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanentdamage to the device. This is a stress rating only and functional operation of the device at theseor any other conditions above those indicated in the operational sections of this specification isnot implied. Exposure to absolute maximum rating conditions for extended periods may affectreliability.

RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)

SymbolVCCVIHVILTA

ParameterSupply VoltageInput High VoltageInput Low Voltage

Commercial Ambient Temperature

5V3.3V5V3.3V5V3.3V

Min.4.53.02.42.0–1.0–0.30

Typ.5.03.3—————

Max.5.53.6VCC + 1.0VCC + 0.30.80.870

UnitVVV°C

CAPACITANCE(1,2)

SymbolCIN1CIN2CIO

Parameter

Input Capacitance: A0-A9

Input Capacitance: RAS, UCAS, LCAS, WE, OEData Input/Output Capacitance: I/O0-I/O15

Max.577

UnitpFpFpF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.2. Test conditions: TA = 25°C, f = 1 MHz.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

ELECTRICAL CHARACTERISTICS(1)

(Recommended Operating Conditions unless otherwise noted.)SymbolParameterIILIIOVOHVOLICC1ICC2ICC3

Input Leakage CurrentOutput Leakage CurrentOutput High Voltage LevelOutput Low Voltage LevelStandby Current: TTLStandby Current: CMOSOperating Current:

Random Read/Write(2,3,4)

Average Power Supply CurrentOperating Current:EDO Page Mode(2,3,4)

Average Power Supply CurrentRefresh Current:RAS-Only(2,3)

Average Power Supply CurrentRefresh Current:CBR(2,3,5)

Average Power Supply CurrentSelf Refresh Current

Test Condition

Any input 0V ≤ VIN ≤ Vcc

Other inputs not under test = 0VOutput is disabled (Hi-Z)0V ≤ VOUT ≤ VccIOH = –5.0 mA (5V)IOH = –2.0 mA (3.3V)IOL = 4.2 mA (5V)IOL = 2.0 mA (3.3V)

RAS, LCAS, UCAS ≥ VIHCommericalRAS, LCAS, UCAS ≥ VCC – 0.2VRAS, LCAS, UCAS,

Address Cycling, tRC = tRC (min.)RAS = VIL, LCAS, UCAS,Cycling tPC = tPC (min.)

RAS Cycling, LCAS, UCAS ≥ VIHtRC = tRC (min.)

RAS, LCAS, UCAS CyclingtRC = tRC (min.)Self Refresh mode

5V3.3V5V3.3V-50-60-50-60-50-60-50-605V3.3VSpeed

Min.–5–52.4———————————————

Max.55—0.42210.51601459080160145160145500300

UnitµAµAVVmAmAmA

ICC4mA

ICC5mA

ICC6mA

ICCSµAµA

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper deviceoperation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.4. Column-address is changed once each EDO page cycle.5. Enables on-chip refresh and address counters.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

AC CHARACTERISTICS(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)SymboltRCtRACtCACtAAtRAStRPtCAStCPtCSHtRCDtASRtRAHtASCtCAHtRADtRALtRSHtRHCPtCLZtCRPtODtOEtOEDtOEHCtOEPtRCStRRHtRCHtWCHtWPtWPZtRWLtCWLtWCS

Parameter

Random READ or WRITE Cycle TimeAccess Time from RAS(6, 7)Access Time from CAS(6, 8, 15)

Access Time from Column-Address(6)RAS Pulse WidthRAS Precharge TimeCAS Pulse Width(26)

CAS Precharge Time(9, 25)CAS Hold Time (21)

RAS to CAS Delay Time(10, 20)Row-Address Setup TimeRow-Address Hold Time

Column-Address Setup Time(20)Column-Address Hold Time(20)

RAS to Column-Address Delay Time(11)Column-Address to RAS Lead TimeRAS Hold Time(27)

RAS Hold Time from CAS PrechargeCAS to Output in Low-Z(15, 29)

CAS to RAS Precharge Time(21)Output Disable Time(19, 28, 29)Output Enable Time(15, 16)

Output Enable Data Delay (Write)OE HIGH Hold Time from CAS HIGHOE HIGH Pulse Width

Read Command Setup Time(17, 20)Read Command Hold Time(referenced to RAS)(12)

Read Command Hold Time(referenced to CAS)(12, 17, 21)

Write Command Hold Time(17, 27)Write Command Pulse Width(17)

WE Pulse Widths to Disable OutputsWrite Command to RAS Lead Time(17)Write Command to CAS Lead Time(17, 21)Write Command Setup Time(14, 17, 20)

-50

Min.Max.84———5030810381208081025835050—20510510088101380

—50132510K—10K——37————25—————1212————————————

-60

Min.Max.104———60401010401401001012301037050—20510510010101015100

—60153010K—10K——45————30—————1515————————————

Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)SymboltOEHtDStDHtRWCtRWDtCWDtAWDtPCtRASPtCPAtPRWCtCOHtOFFtWHZtCSRtCHRtRPCtORDtREFtT

Parameter

OE Hold Time from WE duringREAD-MODIFY-WRITE cycle(18)Data-In Setup Time(15, 22)Data-In Hold Time(15, 22)

READ-MODIFY-WRITE Cycle TimeRAS to WE Delay Time duringREAD-MODIFY-WRITE Cycle(14)CAS to WE Delay Time(14, 20)

Column-Address to WE Delay Time(14)EDO Page Mode READ or WRITECycle Time(24)

RAS Pulse Width in EDO Page ModeAccess Time from CAS Precharge(15)EDO Page Mode READ-WRITECycle Time(24)

Data Output Hold after CAS LOWOutput Buffer Turn-Off Delay fromCAS or RAS(13,15,19, 29)

Output Disable Delay from WE

CAS Setup Time (CBR REFRESH)(30, 20)CAS Hold Time (CBR REFRESH)(30, 21)RAS to CAS Precharge Time

OE Setup Time prior to RAS duringHIDDEN REFRESH Cycle

Auto Refresh Period (1,024 Cycles)Transition Time (Rise or Fall)(2, 3)

-50

Min.Max.80810826392050—565035850—1

————————100K30——1210————1650

-60

Min.Max.100101337732472560—6850351050—1

————————100K35——1510————1650

Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsmsns

AC TEST CONDITIONS

Output load:

Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)One TTL Load and 50 pF (Vcc = 3.3V ±10%)

Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);

VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)

Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

Notes:

1.An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device

operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.2.VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH

and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.

3.In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)

in a monotonic manner.

4.If CAS and RAS = VIH, data output is High-Z.

5.If CAS = VIL, data output may contain data from the last valid READ cycle.6.Measured with a load equivalent to one TTL gate and 50 pF.

7.Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase

by the amount that tRCD exceeds the value shown.8.Assumes that tRCD > tRCD (MAX).

9.If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the

data output buffer, CAS and RAS must be pulsed for tCP.

10.Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD

is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.

11.Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD

is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.12.Either tRCH or tRRH must be satisfied for a READ cycle.

13.tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.

14.tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS > tWCS

(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD > tRWD(MIN), tAWD > tAWD (MIN) and tCWD > tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read fromthe selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go backto VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.15.Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.

16.During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE

WRITE or READ-MODIFY-WRITE is not possible.17.Write command is defined as WE going low.

18.LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure

that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOWand OE is taken back to LOW after tOEH is met.

19.The I/Os are in open during READ cycles once tOD or tOFF occur.20.The first χCAS edge to transition LOW.21.The last χCAS edge to transition HIGH.

22.These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-MODIFY-WRITE cycles.

23.Last falling χCAS edge to first rising χCAS edge.

24.Last rising χCAS edge to next cycle’s last rising χCAS edge.25.Last rising χCAS edge to first falling χCAS edge.26.Each χCAS must meet minimum pulse width.27.Last χCAS to go LOW.

28.I/Os controlled, regardless UCAS and LCAS.

29.The 3 ns minimum is a parameter guaranteed by design.30.Enables on-chip refresh and address counters.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

READ CYCLE

tRCtRAStRPRAStCSHtCRPtRCDtRSHtCAStRRHUCAS/LCAStRADtASRtRAHtASCtRALtCAHADDRESSWERowtRCSColumntRCHtAAtRACtCACtCLZtOFF(1)RowI/OOEOpentOEValid DatatODOpentOESUndefinedDon’t CareNote:

1.tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

EARLY WRITE CYCLE (OE = DON'T CARE)

tRCtRAStRPRAStCSHtCRPtRCDtRSHtCASUCAS/LCAStRADtASRtRAHtASCtRALtCAHADDRESSRowColumntCWLtRWLtWCRtWCStWCHtWPRowWEtDStDHI/OValid DataDon’t Care12Integrated Circuit Solution Inc.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)

tRWCtRAStRPRAStCSHtCRPtRCDtRSHtCASUCAS/LCAStRADtASRtRAHtASCtCAHtRALADDRESSRowtRCSColumntRWDtCWDtAWDRowtCWLtRWLtWPWEtAAtRACtCACtCLZtDStDHI/OOpentOEValid DOUTtODValid DINOpentOEHOEUndefinedDon’t CareIntegrated Circuit Solution Inc.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

EDO-PAGE-MODE READ CYCLE

tRASPtRPRAStCSHtCRPtRCDtCAStCPtPC(1)tCAStCPtRSHtCAStCPUCAS/LCAStRADtASRtASCtCAHtASCtCAHtASCtRALtCAHADDRESSRowtRAHtRCSColumnColumnColumntRCHRowtRRHWEtAAtRACtCACtCLZtCACtCOHtAAtCPAtCACtCLZtAAtCPAtOFFI/OOpentOEValid DataValid DatatOEHCtODValid DatatOEOpentODOEtOEPUndefinedDon’t CareNote:

1.tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Bothmeasurements must meet the tPC specifications.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

EDO-PAGE-MODE EARLY-WRITE CYCLE

tRASPtRPtRHCPRAStCSHtCRPtRCDtCAStCPtPCtCAStCPtRSHtCAStCPUCAS/LCAStRADtASRtASCtCAHtASCtCAHtASCtRALtCAHADDRESSRowtRAHColumntCWLtWCStWCHtWPColumntCWLtWCStWCHtWPColumntCWLtWCStWCHtWPRowWEtRWLtDStDHtDStDHtDStDHI/OOEValid DataValid DataValid DataDon’t CareIntegrated Circuit Solution Inc.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)

tRASPtRPRAStCSHtCRPtRCDtCAStCPtPC / tPRWC(1)tCAStRSHtCPtCAStCPUCAS/LCAS tASRtRAHtRADtASCtRALtCAHtASCtCAHtASCtCAHADDRESSRowtRWDtRCSColumntCWLtWPtAWDtCWDColumntCWLtWPtAWDtCWDColumntRWLtCWLtWPtAWDtCWDRowWEtRACtCACtCLZ tAAtDStDHtAAtCPAtCACtCLZ tDStDHtAAtCPAtCACtCLZ tDHtDSI/OOpentOE DOUTDINtOD tOE DOUTDINtOD tOE DOUTDINtOD tOEH OpenOEUndefinedDon’t CareNote:

1.tPC is for LATE WRITE only. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS torising edge of CAS. Both measurements must meet the tPC specifications.

16Integrated Circuit Solution Inc.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)

tRASPtRPRAStCSHtPCtCRPtRCDtCAStCPtCAS tPC tCPtRSHtCAStCPUCAS/LCAS tASRtRAHtRADtASCtRALtCAHtASCtCAHtASCtCAHADDRESSRowtRCSColumn (A)Column (B)tRCHtWCSColumn (N) tWCHRowWEtRACtCACtAAtCPAtCACtCOH tAAtWHZtDStDHI/OOpentOE Valid Data (A)Valid Data (B)DINOpenOEDon’t CareIntegrated Circuit Solution Inc.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

AC WAVEFORMS

READ CYCLE (With WE-Controlled Disable)

RAStCSHtCRPtRCDtCAStCP UCAS/LCAStRADtASRtRAHtASCtCAHtASCADDRESSWERowtRCSColumntRCHtAAtRACtCACtCLZtRCSColumntWHZtCLZI/OOEOpentOEValid DataOpentODUndefinedDon’t CareRAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)

tRCtRAStRPRAStCRPtRPCUCAS/LCAStASRtRAHADDRESSI/ORowOpenRowDon’t Care18Integrated Circuit Solution Inc.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)

tRPtRAStRPtRASRAStRPCtCPtCHRtCSRtRPCtCSRtCHRUCAS/LCASI/OOpenHIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)

tRAStRPtRASRAStCRPtRCDtRSHtCHRUCAS/LCAStRADtRAHtASCtRALtCAHtASRADDRESSRowColumntAAtRACtCACtCLZtOFF(2)I/OOpentOEtORDValid DataOpentODOEUndefinedDon’t CareNotes:

1.A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.2.tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

SELF REFRESH CYCLE (Addresses : WE and OE = DON'T CARE)

tRPVIHRASVILtRPCtCPVIHUCAS/LCASVILVOHDQVOLtCHDtCSRtRPCtCPtRASStRPSOpenDon’t CareTIMING PARAMETERS

SymboltCHDtCPtCSRtRASStRPtRPStRPC

-50

Min.Max.810510030845

———————

-60

Min.Max.10105100401045

———————

Unitsnsnsnsµsnsnsns

ORDERING INFORMATION: 5VCommercial Range: 0°C to 70°C

Speed (ns)

5060

Order Part No.IC41C16100A-50KIC41C16100A-50TIC41C16100A-60KIC41C16100A-60T

Package400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2

ORDERING INFORMATION: 5VCommercial Range: 0°C to 70°C

Speed (ns)

5060

Order Part No.IC41C16100AS-50KIC41C16100AS-50TIC41C16100AS-60KIC41C16100AS-60T

Package400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2

20Integrated Circuit Solution Inc.

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IC41C16100A/IC41C16100ASIC41LV16100A/IC41LV16100AS

ORDERING INFORMATION: 3.3VCommercial Range: 0°C to 70°C

Speed (ns)

5060

Order Part No.IC41LV16100A-50KIC41LV16100A-50TIC41LV16100A-60KIC41LV16100A-60T

Package400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2

ORDERING INFORMATION: 3.3VCommercial Range: 0°C to 70°C

Speed (ns)

5060

Order Part No.IC41LV16100AS-50KIC41LV16100AS-50TIC41LV16100AS-60KIC41LV16100AS-60T

Package400mil SOJ400mil TSOP-2400mil SOJ400mil TSOP-2

Integrated Circuit Solution Inc.

HEADQUARTER:

NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,

HSIN-CHU, TAIWAN, R.O.C.

TEL: 886-3-5780333Fax: 886-3-5783000

BRANCH OFFICE:

7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.

TEL: 886-2-26962140FAX: 886-2-26962252http://www.icsi.com.tw

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