REF02_05资料

5 V Precision Voltage

Reference/Temperature Transducer

REF02

PIN CONFIGURATIONS

NC8FEATURES

5 V output: ±0.3% maximum

Temperature voltage output: 1.96 mV/°C Adjustment range: ±3% minimum

Excellent temperature stability: 8.5 ppm/°C maximum Low noise: 15 µV p-p maximum

Low supply current: 1.4 mA maximum Wide input voltage range: 7 V to 40 V High load-driving capability: 10 mA No external components Short-circuit proof

NC1VIN2NC347NC6VOUT5TRIMGROUND(CASE)NC = NO CONNECT. DO NOT CONNECT ANYTHINGON THESE PINS. SOME OF THEM ARE RESERVEDFOR FACTORY TESTING PURPOSES.00375-F-00100375-F-00200375-F-003

Figure 1. 8-Lead TO-99 (J-Suffix)

NC18NCNCVOUTTRIMVIN2REF027GENERAL DESCRIPTION

The REF02 precision voltage reference provides a stable 5 V output that can be adjusted over a ±6% range with minimal effect on temperature stability. Single-supply operation over an input voltage range of 7 V to 40 V, low current drain of 1 mA, and excellent temperature stability are achieved with an

improved band gap design. Low cost, low noise, and low power make the REF02 an excellent choice whenever a stable voltage reference is required. Applications include DACs and ADCs, portable instrumentation, and digital voltmeters. The versatility of the REF02 is enhanced by its use as a monolithic temperature transducer. For new designs, refer to the ADR02.

TOP VIEWTEMP3(Not to Scale)GND465NC = NO CONNECT. DO NOT CONNECT ANYTHINGON THESE PINS. SOME OF THEM ARE RESERVEDFOR FACTORY TESTING PURPOSES. Figure 2. 8-Lead PDIP (P-Suffix), 8-Lead CERDIP (Z-Suffix) and 8-Lead SOIC (S-Suffix) NCNCNC1NC32201918NC4VIN5NC6TEMP7NC10111213NCNCNCNCVOUTNCREF02TOP VIEW(Not to Scale)17161514GNDNCNCNC = NO CONNECT. DO NOT CONNECT ANYTHINGON THESE PINS. SOME OF THEM ARE RESERVEDFOR FACTORY TESTING PURPOSES.TRIMNC Figure 3. 20-Terminal LCC (RC-Suffix) OUTPUT RESISTORSREF02 OPTION883C PRODUCTR918kΩR112kΩ4.5kΩR126.1kΩ15kΩQ8Q7Q14Q13R8R7R14Q15R152INPUTP, S, J, Z PACKAGES18kΩQ9Q12Q11C1R6R3R4Q4Q13R1R2*SEE OUTPUT RESISTORSR5Q2Q20Q3Q10Q6Q5R13Q17Q21Q18Q16Q196R12*R9*OUTPUT≈1.23VR11*5TRIM4GROUND00375-F-004TEMPR10Figure 4. Simplified Schematic Rev. I

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

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TABLE OF CONTENTS

Features..............................................................................................1 General Description.........................................................................1 Pin Configurations...........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Electrical Specifications...............................................................3 Absolute Maximum Ratings............................................................7 Thermal Resistance......................................................................7 ESD Caution..................................................................................7

Typical Performance Characteristics..............................................8 Output Adjustment........................................................................10 Temperature Monitoring...........................................................11 Reference Stack with Excellent Line Regulation....................11 Precision Current Source..........................................................12 Supply Bypassing........................................................................12 Outline Dimensions.......................................................................13 Ordering Guide..........................................................................15

REVISION HISTORY

12/05—Rev. H to Rev. I

Changes to Figure 14......................................................................10 Changes to Ordering Guide..........................................................15 5/05—Rev. G to Rev. H

Updated Figure 4..............................................................................1 Changes to Specifications................................................................3 Updated Outline Dimensions.......................................................13 Changes to Ordering Guide..........................................................15 2/05—Rev. F to Rev. G

Changes to Specifications................................................................3 Change to Outline Dimensions....................................................13 7/04—Rev. E to Rev. F

Updated Format..................................................................Universal Changes to Simplified Schematic...................................................1 Changes to Specifications................................................................3 Changes to Specifications................................................................4 Changes to Specifications................................................................5 Changes to Specifications................................................................6 Changes to Figure 18......................................................................10 Changes to Ordering Guide..........................................................15 3/04—Rev. D to Rev. E

Changes to Features..........................................................................1 Changes to Specifications................................................................2 Changes to Ordering Guide............................................................4 Replaced TPCs 3 and 4....................................................................5 Added Temperature Monitoring section ......................................7 Updated Figure 5 .............................................................................7 Deleted Table I..................................................................................7 Updated Figure 6 .............................................................................7

10/03—Rev. C to Rev. D

Updated TPCs.....................................................................Universal Changes to Features .........................................................................1 Changes to Electrical Specifications ..............................................2 Change to Absolute Maximum Ratings ........................................4 Changes to Ordering Guide.............................................................4 Deleted Typical Electrical Characteristics table........................... 4 Deleted Wafer Test Limits................................................................4 Deleted Figure 1.................................................................................4 10/02—Rev. B to Rev. C

Changes to Features..........................................................................1 Changes to General Description.....................................................1 Changes to Simplified Schematic....................................................1 Changes to Specifications.................................................................2 Changes to Absolute Maximum Ratings .......................................5 Changes to Package Type ................................................................5 Changes to Ordering Guide.............................................................5 Updated to Outline Dimensions..................................................11

Rev. I | Page 2 of 16

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SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

@ VIN = 15 V, TA = 25°C, unless otherwise noted. Table 1.

Parameter Output Voltage

Output Adjustment Range Output Voltage Noise1 P, Z, and S Packages J Package 883 Parts Line Regulation2Load Regulation2

Turn-On Settling Time1 Quiescent Supply Current Load Current Sink Current3

Short-Circuit Current

Temperature Voltage Output4

883C Product

P, S, J, and Z Packages

Guaranteed by design.

Line and load regulation specifications include the effect of self-heating. 3

During sink current test, the device meets the output voltage specified. 4

Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.

12

Symbol VO ∆VTRIM en p-p

tON ISY IL IS ISC VTVTConditions IL = 0 mA RP = 10 kΩ 0.1 Hz to 10 Hz

VIN = 8 V to 40 V IL = 0 mA to 10 mA To ±0.1% of final value No load

VO = 0

REF02A/REF02E REF02/REF02H Unit Min Typ Max Min Typ Max

4.985 5.000 5.015 4.975 5.000 5.025 V ±3 ±6 ±3 ±6 % 15 15 µV p-p 20 20 µV p-p 10 15 10 15 µV p-p 0.006 0.010 0.006 0.010 %/V 0.005 0.010 0.006 0.010 %/mA 5 5 µs 1.0 1.4 1.0 1.4 mA 10 10 mA −0.3 –0.5 –0.3 –0.5 mA 30 30 mA 630 630 mV 550 550 mV Rev. I | Page 3 of 16

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REF02

@ VIN = 15 V, −55°C ≤ TA ≤ +125°C for REF02A and REF02; 0°C ≤ TA ≤ 70°C for REF02E and REF02H; IL = 0 mA, unless otherwise noted. Table 2.

Parameter

Output Voltage Change with Temperature1, 2

Output Voltage Temperature Coefficient3Change in VO Temperature Coefficient with Output Adjustment Line Regulation VIN = 8 V to 40 V4 Load Regulation IL = 0 mA to 8 mA4

Temperature Voltage Output Temperature Coefficient5 883C Product

P, S, J, and Z Packages

ΔVOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed as a percentage of 5 V.

−VMINV

∆VOT=MAX×100

5V

2

∆VOT specification applies trimmed to 5,000 V or untrimmed. 3

TCVO is defined as ∆VOT divided by the temperature range.

∆VOT

TCVO=

70°C

4

Line and load regulation specifications include the effect of self-heating. 5

Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.

1

Symbol ∆VOTTCVO TCVT

Conditions 0°C ≤ TA ≤ 70°C

−55°C ≤ TA ≤ +125°C RP = 10 kΩ 0°C ≤ TA ≤ 70°C

−55°C ≤ TA ≤ +125°C 0°C ≤ TA ≤ 70°C

−55°C ≤ TA ≤ +125°C

REF02A/REF02E REF02/REF02H Min Typ Max Min Typ Max Unit 0.02 0.06 0.07 0.17 % 0.06 0.15 0.18 0.45 % 3 8.5 10 25 ppm/°C

0.7

0.7

ppm/%

0.007 0.012

0.009 0.015 0.006 0.010 0.007 0.012 0.007 0.012 %/V

0.009 0.015 %/V 0.007 0.012 %/mA 0.009 0.015 %/mA

2.10 2.10 mV/°C

1.96 1.96 mV/°C

Rev. I | Page 4 of 16

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@ VIN = 15 V, TA = 25°C, unless otherwise noted. Table 3.

Parameter Output Voltage

Output Adjustment Range Output Voltage Noise1 P, Z, and S Packages J Package 883 Parts Line Regulation2Load Regulation2

Turn-On Settling Time1 Quiescent Supply Current Load Current Sink Current3

Short-Circuit Current

Temperature Voltage Output4

883C Product

P, S, J, and Z Packages

Guaranteed by design.

Line and load regulation specifications include the effect of self-heating. 3

During sink current test, the device meets the output voltage specified. 4

Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.

1 2

Symbol VO ∆VTRIM en p-p

tON ISY IL IS ISC VTVT

Conditions IL = 0 mA RP = 10 kΩ 0.1 Hz to 10 Hz

VIN = 8 V to 40 V IL = 0 mA to 8 mA IL = 0 mA to 4 mA

To ±0.1% of final value No load

VO = 0

REF02C REF02D Min Typ Max Min Typ Max Unit 4.950 5.000 5.050 4.900 5.000 5.100 V ±2.7 ±6.0 ±2.0 ±6.0 % 15 µV p-p 20 15 µV p-p 12 18 20 µV p-p 0.009 0.015 0.010 0.04 %/V 0.006 0.015 %/mA 0.015 0.04 %/mA 5 5 µs 1.0 1.6 1.0 2.0 mA 8 8 mA −0.3 −0.5 −0.3 −0.5 mA 30 30 mA 630 630 mV 550 550 mV

Rev. I | Page 5 of 16

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REF02

@ VIN = 15 V, IL = 0 mA, 0°C ≤ TA ≤ 70°C for REF02CJ, REF02CZ, and REF02DP; and −40°C ≤ TA ≤ +85°C for REF02CP and REF02CS, unless otherwise noted. Table 4.

Parameter

Output Voltage Change with Temperature1, 2

Output Voltage Temperature Coefficient3 Change in VO Temperature Coefficient with Output Adjustment Line Regulation4 Load Regulation4 Temperature Voltage Output Temperature Coefficient5 883C Product P, S, J, and Z Packages

ΔVOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed as a percentage of 5 V.

V−VMIN

∆VOT=MAX×100

5V

2

∆VOT specification applies trimmed to 5,000 V or untrimmed. 3

TCVO is defined as ΔVOT divided by the temperature range.

∆VOT

TCVO=

70°C

4

Line and load regulation specifications include the effect of self-heating. 5

Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.

1

Symbol ∆VOTTCVO

TCVT

Conditions RP = 10 kΩ VIN = 8 V to 40 V IL = 0 mA to 5 mA

REF02C REF02D Min Typ Max Min Typ Max Unit 0.14 0.45 0.49 1.7 % 20 65 70 250 ppm/°C 0.7 0.7 ppm/% 0.011 0.018 0.012 0.05 %/V 0.008 0.018 0.016 0.05 %/mA 2.10 2.10 mV/°C 1.96 1.96 mV/°C

Rev. I | Page 6 of 16

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Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating1Input Voltage 40 V

Indefinite Output Short-Circuit Duration

to Ground or VINStorage Temperature Range J, RC, and Z Packages P Package

Operating Temperature Range REF02A, REF02J, REF02RC REF02CJ, REF02CZ

REF02CP, REF02CS, REF02E, and REF02H Lead Temperature Range (Soldering 10 sec)

–65°C to +150°C –65°C to +125°C

–55°C to +125°C 0°C to 70°C –40°C to +85°C 300°C

THERMAL RESISTANCE

Table 6.

Package Type TO-99 (J)

8-Lead CERDIP (Z) 8-Lead PDIP (P)

20-Terminal Ceramic LCC (RC) 8-Lead SOIC (S)

1

1

Absolute maximum ratings apply to both DICE packaged parts, unless otherwise noted.

θJA1170 162 110 120 160 θJC24 26 50 40 44 Unit °C/W °C/W °C/W °C/W °C/W

θJA is specified for worst-case mounting conditions; device in socket for TO, CERDIP, PDIP, and LCC packages; and device soldered to printed circuit board for SOIC package.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. I | Page 7 of 16

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REF02

20TA = 25°CMAXIMUM LOAD CURRENT (mA)00375-F-005TYPICAL PERFORMANCE CHARACTERISTICS

10kVIN = 15VTA = 25°C19OUTPUT NOISE (µV p-p)1k18171001610101001k10kFREQUENCY (Hz)100k1M141015

202530INPUT VOLTAGE (V)3000375-F-00815

Figure 5. Output Wideband Noise vs. Bandwidth

(0.1 Hz to Frequency Indicated)

766656362616010VIN = 15VTA = 25°C0.00310.0100LOAD REG–T/LOAD REG (25°C)Figure 8. Maximum Load Current vs. Input Voltage

1.4VIN = 15V1.31.21.11.00.90.80.70.6–6000375-F-009LINE REGULATION (dB)0.03100.10000.31001.00003.100010.00001M00375-F-006LINE REGULATION (%/V)1001k10kFREQUENCY (Hz)100k–40–200

20406080TEMPERATURE (°C)100120140

Figure 6. Line Regulation vs. Frequency Figure 9. Normalized Load Regulation (∆IL = 10 mA) vs. Temperature

0.016PERCENT CHANGE IN OUTPUT VOLTAGE (%)1.4VIN = 15V0.014LINE REG–T/LINE REG (25°C)0.0120.0100.0080.0060.00400375-F-0071.31.21.11.00.90.80.70.6–6000375-F-0100.0020–1025°CDEVICE IMMERSEDIN 75°C OIL BATH01020TIME (s)304050–40–200

20406080TEMPERATURE (°C)100120140

Figure 7. Output Change Due to Thermal Shock Figure 10. Normalized Line Regulation vs. Temperature

Rev. I | Page 8 of 16

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0.03TA = 25°CAXIMUM LOAD CURRENT (mA)REF02

30VIN = 15V25LINE REGULATION (%/V)0.0220150.0110M110-F-57300051015202530INPUT VOLTAGE (V)

Figure 11. Line Regulation vs. Input Voltage 1.3

VIN = 15V1.2)A(m T1.1NRERUC1.0 TNCES0.9IEUQ0.8620-F-5730.700–60–40–20020406080100120140TEMPERATURE (°C)

Figure 12. Quiescent Current vs. Temperature

Rev. I | Page 9 of 16

5210-F-573000–60–40–20020406080100120140TEMPERATURE (°C)

Figure 13. Maximum Load Current vs. Temperature

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REF02

Adjustment of the output does not significantly affect the temperature performance of the device. The temperature

coefficient change is approximately 0.7 ppm/°C for 100 mV of output adjustment.

OUTPUT ADJUSTMENT

The REF02 trim terminal can be used to adjust the output voltage over a 5 V ± 300 mV range. This feature lets the system designer trim system errors by setting the reference to a voltage other than 5 V. The output also can be set to exactly 5.00 V or to 5.12 V for binary applications.

U1REF02VINVINVOUTVOTEMPTRIMpotGNDR110kΩ470kΩR21kΩ720-57300Figure 14. Output Adjustment Circuit

+18V2VINREF02GND4410-F-5–18V7300 Figure 15. Burn-In Circuit +15V2VIN+5VV6OREF0210kΩ3TEMPTRIM5GND10kΩ4+15V0.1µF–5V5kΩOP02510-F5-7–15V300Figure 16. ±5 V Reference V+5V+2.5VO+26R15.6kΩREF02VREFR25.6kΩ47–26OP02VR1O+ =R1+ R2(VREF),VR2O– =R1+ R2(VREF)4+3+V–9V–2.5VOFigure 17. ±2.5 V Reference Rev. I | Page 10 of 16

610-F-57300

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REF02

V+ (12V TO 32V)R727kΩ2VINVOHEATINGELEMENTR1(9.2kΩ)R3(1.3kΩ)R21.5kΩR62+TEMPERATURE MONITORING

The REF02 provides a TEMP output (Pin 3) that varies linearly with temperature. This output can be used to monitor the temperature change in the system. The voltage at VTEMP is

approximately 550 mV at 25°C, and the temperature coefficient is approximately 1.96 mV/°C (see Figure 18).

850800750VIN = 9VSAMPLE SIZE = 663REF02TEMPGND(SEE NOTE 1)43–CMP02V–418V+7TEMP PIN OUTPUT (mV)Z PACKAGE AND 833 PRODUCT700650600550J, S, AND P PACKAGES500450400–5000375-F-017R52.2kΩ∆VTEMP/∆T = 2.1mV/°CR42.7kΩ∆VTEMP/∆T = 1.96mV/°C00375-F-019NOTES1.REF02 SHOULD BE THERMALLY CONNECTEDTO SUBSTANCE BEING HEATED.2.NUMBERS IN PARENTHESES ARE FOR ASETPOINT TEMPERATURE OF 60°C.3.R3 = R1|| R2|| R6

Figure 20. Temperature Controller

REFERENCE STACK WITH EXCELLENT LINE REGULATION

–250255075TEMPERATURE (°C)100125Figure 18. Voltage at TEMP Pin vs. Temperature

A voltage change of 39.2 mV at the TEMP pin corresponds to a 20°C change in temperature.

The TEMP function is provided as a convenience rather than a precise feature. Since the voltage at the TEMP node is acquired from the band gap core, current pulling from this pin has a significant effect on VOUT. Care must be taken to buffer the TEMP output with a suitable low bias current op amp, such as the AD8601, AD820, or OP1177. Using any of these three op amps results in less than a 100 µV change in ΔVOUT (see

Figure 19). Without buffering, even tens of microamps drawn from the TEMP pin can cause VOUT to fall out of specification.

U115VVINV+U2Two REF01s and one REF02 can be stacked to yield 5.00 V, 15.00 V, and 25.00 V outputs. An additional advantage is near-perfect line regulation of the 5.0 V and 15.0 V output. A 27 V to 55 V input change produces an output change that is less than the noise voltage of the devices. A load bypass resistor (RB) provides a path for the supply current (ISY) of the 15.00 V regulator.

In general, any number of REF01s and REF02s can be stacked this way. For example, 10 devices yield 10 outputs in 5 V or 10 V steps. The line voltage can change from 100 V to 130 V. Care must be taken, however, to ensure that the total load currents do not exceed the maximum usable current (typically 21 mA).

27V TO 55V2VINVO615VREF02VINTEMPVOUTTRIM00375-F-018REF02VOTRIMGND42VINVO610V510kΩVTEMP1.9mV/°COP1177V–GND

Figure 19. Temperature Monitoring

2VINVO6REF02TRIMGND4510kΩ5VREF02TRIMGND400375-F-020510kΩRB6.8kΩ

Figure 21. Reference Stack

Rev. I | Page 11 of 16

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REF02

SUPPLY BYPASSING

For best results, it is recommended that the power supply pin be bypassed with a 0.1 µF disc ceramic capacitor.

IOUT2VINVOVOLTAGE COMPLIANCE:–9V TO +25V6PRECISION CURRENT SOURCE

A current source with 35 V output compliance and excellent output impedance can be obtained using this circuit. REF02 keeps the line voltage and power dissipation constant in the device; the only important error consideration at room

temperature is the negative supply rejection of the op amp. The typical 3 µV/V PSRR of the OP02E creates a 20 ppm change (3 µV/V × 35 V/5 V) in output current over a 25 V range. For example, a 5 mA current source can be built (R = 1 kΩ) with 350 MΩ output impedance.

+50V35VRO=20×10–6×5mA6VO2VINREF023TEMPTRIM5RIOUT = +GND45V+ 1mAR–15V00375-F-023

REF0222VINVO6GND4Figure 24. Current Sink

5kΩ+15VMSBLSB5kΩ+15V2R(TRIM FORCALIBRATION)REF021GND4CRCVINVO0.1µF655kΩB1B2B3B4B5B6B7B8lO42REF02GND4DAC08V–V+5kΩ+15VCCVLClOOP02EO–15V–15V00375-F-024

7623VO= 0VTO 25VFigure 25. DAC Reference

+7.5V (±10%)200375-F-021OP02E4+7.5V–5V5VIO=RVIN

VO6R120kΩR213.3kΩA1VO(+) = +3VREF02HJGND4Figure 22. Precision Current Source

15V2VINVO61/2 OP04CKREF023TEMPTRIM5RIOUT = +GND–7.5V–7.5V5V+ 1mAR1/2 OP04CKR42kΩ00375-F-022A2R31kΩVO(–) =–3V4VOLTAGE COMPLIANCE:–25V TO +8VIOUT–7.5V (±10%)00375-F-025

Figure 23. Current Source

Figure 26. ±3 V Reference

Rev. I | Page 12 of 16

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REF02

0.005 (0.13)MIN8OUTLINE DIMENSIONS

0.055 (1.40)MAX5REFERENCE PLANE0.310 (7.87)0.220 (5.59)140.1850 (4.70)0.1650 (4.19)0.5000 (12.70)MIN0.2500 (6.35) MIN0.0500 (1.27) MAX0.1000 (2.)BSC 50.100 (2.) BSC0.3700 (9.40)0.3350 (8.51)0.3350 (8.51)0.3050 (7.75)0.1600 (4.06)0.1400 (3.56)670.405 (10.29) MAX0.200 (5.08)MAX0.200 (5.08)0.125 (3.18)0.023 (0.58)0.014 (0.36)0.070 (1.78)0.030 (0.76)0.060 (1.52)0.015 (0.38)0.150 (3.81)MINSEATINGPLANE15° 0°0.320 (8.13)0.290 (7.37)40.2000(5.08)BSC0.1000(2.)BSC 320.0190 (0.48)0.0160 (0.41)0.0210 (0.53)0.0160 (0.41)BASE & SEATING PLANE180.0450 (1.14)0.0270 (0.69)0.0400 (1.02) MAX0.015 (0.38)0.008 (0.20)0.0400 (1.02)0.0100 (0.25)0.0340 (0.86)0.0280 (0.71)45° BSCCONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MO-002-AKCONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 27. 8-Lead Ceramic Dual In-Line Package [CERDIP]

Z-Suffix (Q-8)

Dimensions shown in inches and (millimeters) Figure 29. 8-Lead Metal Header Package [TO-99]

J-Suffix (H-08)

Dimensions shown in inches and (millimeters)

0.400 (10.16)0.365 (9.27)0.355 (9.02)815

40.280 (7.11)0.250 (6.35)0.240 (6.10)PIN 10.100 (2.)BSC0.210(5.33)MAX0.150 (3.81)0.130 (3.30)0.115 (2.92)0.022 (0.56)0.018 (0.46)0.014 (0.36)0.070 (1.78)0.060 (1.52)0.045 (1.14)0.060 (1.52)MAX0.015(0.38)MIN0.325 (8.26)0.310 (7.87)0.300 (7.62)0.195 (4.95)0.130 (3.30)0.115 (2.92)0.015 (0.38)GAUGEPLANESEATINGPLANE0.430 (10.92)MAX0.100 (2.)0.0 (1.63)0.075 (1.91)REF0.095 (2.41)0.075 (1.90)191820140.014 (0.36)0.010 (0.25)0.008 (0.20)30.200 (5.08)REF0.100 (2.) REF0.015 (0.38)MIN0.028 (0.71)0.022 (0.56)0.050 (1.27)BSC0.005 (0.13)MIN0.358 (9.09)0.342 (8.69)SQ0.358(9.09)MAXSQ0.011 (0.28)0.007 (0.18)R TYP0.075 (1.91)REF0.055 (1.40)0.045 (1.14)BOTTOMVIEW14130.088 (2.24)0.0 (1.37)45° TYP0.150 (3.81)BSCCOMPLIANT TO JEDEC STANDARDS MS-001-BACONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 28. 8-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body P-Suffix (N-8)

Dimensions shown in inches and (millimeters)

Figure 30. 20-Terminal Ceramic Leadless Chip Carrier [LCC]

RC-Suffix (E-20A)

Dimensions shown in inches and (millimeters)

Rev. I | Page 13 of 16

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5.00 (0.1968)4.80 (0.10)84.00 (0.1574)3.80 (0.1497)16.20 (0.2440)5.80 (0.2284)1.27 (0.0500)BSC0.25 (0.0098)0.10 (0.0040)1.75 (0.0688)1.35 (0.0532)0.50 (0.0196)× 45°0.25 (0.0099)0.51 (0.0201)COPLANARITYSEATING0.31 (0.0122)0.10PLANE8°0.25 (0.0098)0°1.27 (0.0500)0.40 (0.0157)0.17 (0.0067)COMPLIANT TO JEDEC STANDARDS MS-012-AACONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 31. 8-Lead Standard Small Outline Package [SOIC]

Narrow Body S-Suffix (R-8)

Dimensions shown in millimeters and (inches)

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TA = 25°C

ORDERING GUIDE

Model

REF02AJ/883C1 REF02AZ

REF02AZ/883C1 REF02CJ REF02CP REF02CPZ2REF02CS

REF02CS-REEL REF02CS-REEL7 REF02CSZ2

REF02CSZ-REEL2 REF02CSZ-REEL72 REF02CZ REF02DP REF02DPZ2 REF02EJ REF02EZ REF02J REF02HJ REF02HZ REF02HP REF02HPZ2 REF02HS REF02HSZ2 REF02RC/8831 REF02Z

12

∆VOS Max (mV)

±15 ±15 ±15 ±50 ±50 ±50 ±50 ±50 ±50 ±50 ±50 ±50 ±50 ±100 ±100 ±15 ±15 ±25 ±25 ±25 ±25 ±25 ±25 ±25 ±25 ±25

Temperature Range −55°C to +125°C −55°C to +125°C −55°C to +125°C 0°C to 70°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 0°C to 70°C 0°C to 70°C 0°C to 70°C −40°C to +85°C −40°C to +85°C −55°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −55°C to +125°C −55°C to +125°C

Package Description 8-Lead TO-99 8-Lead CERDIP 8-Lead CERDIP 8-Lead TO-99 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead CERDIP 8-Lead PDIP 8-Lead PDIP 8-Lead TO-99 8-Lead CERDIP 8-Lead TO-99 8-Lead TO-99 8-Lead CERDIP 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC 8-Lead SOIC 20-Lead LCC 8-Lead CERDIP

Package Option J-Suffix (H-08) Z-Suffix (Q-8) Z-Suffix (Q-8) J-Suffix (H-08) P-Suffix (N-8) P-Suffix (N-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) Z-Suffix (Q-8) P-Suffix (N-8) P-Suffix (N-8) J-Suffix (H-08) Z-Suffix (Q-8) J-Suffix (H-08) J-Suffix (H-08) Z-Suffix (Q-8) P-Suffix (N-8) P-Suffix (N-8) S-Suffix (R-8) S-Suffix (R-8) RC-Suffix (E-20A) Z-Suffix (Q-8)

Consult sales for 883 data sheet. Z = Pb-free part.

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NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00375-0-12/05(I)

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