MEMORY存储芯片MT48LC16M16A2-6A中文规格书

READ Operation

4.BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0.

BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8.

5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

READ Operation Followed by PRECHARGE Operation

The minimum external READ command to PRECHARGE command spacing to the samebank is equal to AL + tRTP with tRTP being the internal READ command to PRECHARGEcommand delay. Note that the minimum ACT to PRE timing, tRAS, must be satisfied aswell. The minimum value for the internal READ command to PRECHARGE commanddelay is given by tRTP (MIN) = MAX (4 × nCK, 7.5ns). A new bank ACTIVATE commandmay be issued to the same bank if the following two conditions are satisfied simultane-ously:

•The minimum RAS precharge time (tRP [MIN]) has been satisfied from the clock atwhich the precharge begins.

•The minimum RAS cycle time (tRC [MIN]) from the previous bank activation has beensatisfied.

Figure 150: READ to PRECHARGE with 1tCK Preamble

T0

CK_cCK_tT1

T2

T3

T6

T7

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

CommandDESREADDESDESDESPREDESDESDESDESDESDESDESDESACTDESDESDESBank Group

Address

BGaBGa or BGbBGaAddress

Bank aCol ntRTPBank a(or all)tRPBank aRow bRL = AL + CLBC4 OpertaionDQS_t,DQS_cDQ

BL8 OpertaionDQS_t,DQS_cDOnDOn + 1DOn + 2DOn + 3DQ

DOnDOn + 1DOn + 2DOn + 3DOn + 4DOn + 5DOn + 6DOn + 7Time Break Transitioning DataDon’t CareNotes:

1.RL = 11 (CL = 11, AL = 0 ), Preamble = 1tCK, tRTP = 6, tRP = 11.2.DO n = data-out from column n.

3.DES commands are shown for ease of illustration; other commands may be valid at

these times.

4.The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T7)

and that tRC (MIN) is satisfied at the next ACTIVATE command time (T18).5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

4Gb: x8, x16 Automotive DDR4 SDRAM

READ Operation

Figure 151: READ to PRECHARGE with 2tCK Preamble

T0CK_cCK_tT1T2T3T6T7T10T11T12T13T14T15T16T17T18T19T20T21CommandDESREADDESDESDESPREDESDESDESDESDESDESDESDESACTDESDESDESBank Group

Address

BGaBGa orBGbBGaAddress

Bank aCol ntRTPBank a(or all)tRPBank aRow bRL = AL + CLBC4 OpertaionDQS_t,DQS_cDQ

BL8 OpertaionDQS_t,DQS_cDOnDOn + 1DOn + 2DOn + 3DQ

DOnDOn + 1DOn + 2DOn + 3DOn + 4DOn + 5DOn + 6DOn + 7Time Break Transitioning DataDon’t CareNotes:

1.RL = 11 (CL = 11, AL = 0 ), Preamble = 2tCK, tRTP = 6, tRP = 11.2.DO n = data-out from column n.

3.DES commands are shown for ease of illustration; other commands may be valid at

these times.

4.The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T7)

and that tRC (MIN) is satisfied at the next ACTIVATE command time (T18).5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 152: READ to PRECHARGE with Additive Latency and 1tCK Preamble

T0CK_cCK_tT1T2T3T10T11T12T13T16T19T20T21T22T23T24T25T26T27CommandDESREADDESDESDESDESDESDESPREDESDESDESDESDESDESDESDESACTBank Group

Address

BGaBGa orBGbBGaAddress

Bank aCol nBank a(or all)Bank aRow btRPAL = CL - 2 = 9tRTPCL = 11BC4 OpertaionDQS_t,DQS_cDQ

BL8 OpertaionDQS_t,DQS_cDOnDOn + 1DOn + 2DOn + 3DQ

DOnDOn + 1DOn + 2DOn + 3DOn + 4DOn + 5DOn + 6DOn + 7Time Break Transitioning DataDon’t CareNotes:

1.RL =20 (CL = 11, AL = CL - 2), Preamble = 1tCK, tRTP = 6, tRP = 11.2.DO n = data-out from column n.

4Gb: x8, x16 Automotive DDR4 SDRAM

READ Operation

3.DES commands are shown for ease of illustration; other commands may be valid at

these times.

4.The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time

(T16) and that tRC (MIN) is satisfied at the next ACTIVATE command time (T27).5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 153: READ with Auto Precharge and 1tCK Preamble

T0CK_cCK_tT1T2T3T6T7T10T11T12T13T14T15T16T17T18T19T20T21CommandDESRDADESDESDESPREDESDESDESDESDESDESDESDESACTDESDESDESBank Group

Address

BGaBGa orBGbBGaAddress

Bank aCol ntRTPBank aCol ntRPBank aRow bRL = AL + CLBC4 OpertaionDQS_t,DQS_cDQ

BL8 OpertaionDQS_t,DQS_cDOnDOn + 1DOn + 2DOn + 3DQ

DOnDOn + 1DOn + 2DOn + 3DOn + 4DOn + 5DOn + 6DOn + 7Time Break Transitioning DataDon’t CareNotes:

1.RL = 11 (CL = 11, AL = 0 ), Preamble = 1tCK, tRTP = 6, tRP = 11.2.DO n = data-out from column n.

3.DES commands are shown for ease of illustration; other commands may be valid at

these times.

4.tRTP = 6 setting activated by MR0[A11:9 = 001].

5.The example assumes that tRC (MIN) is satisfied at the next ACTIVATE command time

(T18).

6.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.