DS90CR286A/DS90CR216A+3.3VRisingEdgeDataStrobeLVDSReceiver28-BitChannelLink—66MHz,+3.3VRisingEdgeDataStrobeLVDSReceiver21-BitChannelLink—66MHzJuly2004
DS90CR286A/DS90CR216A
+3.3VRisingEdgeDataStrobeLVDSReceiver28-BitChannelLink—66MHz,+3.3VRisingEdgeStrobeLVDSReceiver21-BitChannelLink—66MHz
GeneralDescription
TheDS90CR286AreceiverconvertsthefourLVDSdatastreams(Upto1.848Gbpsthroughputor231Megabytes/secbandwidth)backintoparallel28bitsofCMOS/TTLdata.AlsoavailableistheDS90CR216AthatconvertsthethreeLVDSdatastreams(Upto1.386Gbpsthroughputor173Megabytes/secbandwidth)backintoparallel21bitsofCMOS/TTLdata.BothReceivers’outputsareRisingedgestrobe.
BothdevicesareofferedinTSSOPpackages.
TheDS90CR286A/DS90CR216Adevicesareenhancedoverpriorgenerationreceiversandprovidedawiderdatavalidtimeonthereceiveroutput.
ThischipsetisanidealmeanstosolveEMIandcablesizeproblemsassociatedwithwide,highspeedTTLinterfaces.
Features
nnnnnnnnnn
20to66MHzshiftclocksupport
50%dutycycleonreceiveroutputclock
Best–in–ClassSet&HoldTimesonRxOUTPUTs
Rxpowerconsumption<270mW(typ)@66MHzWorstCase
RxPower-downmode<200µW(max)ESDrating>7kV(HBM),>700V(EIAJ)PLLrequiresnoexternalcomponents
CompatiblewithTIA/EIA-644LVDSstandardLowprofile56-leador48-leadTSSOPpackageOperatingTemperature:−40˚Cto+85˚C
BlockDiagrams
DS90CR286A
DS90CR216A
10087331
OrderNumberDS90CR216AMTDSeeNSPackageNumberMTD48
10087330
OrderNumberDS90CR286AMTDSeeNSPackageNumberMTD56
TRI-STATE®isaregisteredtrademarkofNationalSemiconductorCorporation.
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DS90CR286A/DS90CR216AAbsoluteMaximumRatings(Note1)
IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheNationalSemiconductorSalesOffice/Distributorsforavailabilityandspecifications.SupplyVoltage(VCC)CMOS/TTLOutputVoltageLVDSReceiverInputVoltageJunctionTemperatureStorageTemperatureLeadTemperature(Soldering,4sec)
MTD56(TSSOP)Package:DS90CR286AMTDMTD48(TSSOP)Package:DS90CR216AMTDPackageDerating:
1.89W1.61W−0.3Vto+4V
−0.3Vto(VCC+0.3V)−0.3Vto(VCC+0.3V)
+150˚C
−65˚Cto+150˚C
+260˚C
DS90CR286AMTDDS90CR216AMTDESDRating
(HBM,1.5kΩ,100pF)(EIAJ,0Ω,200pF)
12.4mW/˚Cabove+25˚C15mW/˚Cabove+25˚C
>7kV>700V
RecommendedOperatingConditions
MinNomMaxUnits
SupplyVoltage(VCC)OperatingFreeAirTemperature(TA)ReceiverInputRangeSupplyNoiseVoltage(VCC)
−40+25+850
2.4100
˚CVmVPP3.0
3.3
3.6
V
MaximumPackagePowerDissipationCapacity@25˚C
ElectricalCharacteristics
Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.SymbolVIHVILVCLIINParameter
HighLevelInputVoltageLowLevelInputVoltageInputClampVoltageInputCurrent
ICL=−18mAVV
CMOS/TTLDCSPECIFICATIONSVOHVOLIOSVTHVTLIINHighLevelOutputVoltageLowLevelOutputVoltageOutputShortCircuitCurrentDifferentialInputHighThresholdDifferentialInputLowThresholdInputCurrent
VV
RECEIVERSUPPLYCURRENTICCRW
ReceiverSupplyCurrentWorstCase
CL=8pF,WorstCasePattern,DS90CR286A(Figures1,2),
TA=−10˚Cto+70˚CCL=8pF,WorstCasePattern,DS90CR286A(Figures1,2),
TA=−40˚Cto+85˚CCL=8pF,WorstCasePattern,DS90CR216A(Figures1,2),
TA=−10˚Cto+70˚CCL=8pF,WorstCasePattern,DS90CR216A(Figures1,2),
TA=−40˚Cto+85˚C
f=33MHzf=37.5MHzf=66MHzf=40MHzf=66MHzf=33MHzf=37.5MHzf=66MHzf=40MHzf=66MHz
49538153814953785378
6570105701055560906090
mAmAmAmAmAmAmAmAmAmA
ININININConditionsMin2.0GND
TypMaxVCC0.8
UnitsVVVµAµAV
CMOS/TTLDCSPECIFICATIONS(ForPowerDownPin)
−0.79+1.8
−102.7
03.30.06−60
−1.5+10
=0.4V,2.5VorVCC=GND
IOH=−0.4mAIOL=2mAVOUT=0VV
CM0.3−120+100
VmAmVmVµAµA
LVDSRECEIVERDCSPECIFICATIONS
=+1.2V
−100
=+2.4V,VCC=3.6V=0V,VCC=3.6V
±10±10
ICCRWReceiverSupplyCurrentWorstCase
ICCRWReceiverSupplyCurrentWorstCase
ICCRWReceiverSupplyCurrentWorstCase
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DS90CR286A/DS90CR216AElectricalCharacteristics
SymbolICCRZ
Parameter
ReceiverSupplyCurrentPowerDown
RECEIVERSUPPLYCURRENT
(Continued)
Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.
Conditions
PowerDown=Low
ReceiverOutputsStayLowduringPowerDownMode
Note1:“AbsoluteMaximumRatings”arethosevaluesbeyondwhichthesafetyofthedevicecannotbeguaranteed.Theyarenotmeanttoimplythatthedeviceshouldbeoperatedattheselimits.Thetablesof“ElectricalCharacteristics”specifyconditionsfordeviceoperation.
Note2:TypicalvaluesaregivenforVCC=3.3VandTA=+25C.
Note3:Currentintodevicepinsisdefinedaspositive.Currentoutofdevicepinsisdefinedasnegative.Voltagesarereferencedtogroundunlessotherwisespecified(exceptVODand∆VOD).
MinTyp10
Max55
UnitsµA
ReceiverSwitchingCharacteristics
OverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecifiedSymbolCLHTCHLTRSPos0RSPos1RSPos2RSPos3RSPos4RSPos5RSPos6RSPos0RSPos1RSPos2RSPos3RSPos4RSPos5RSPos6RSKMRCOPRCOHRCOLRSRCRHRCRCOHRCOLRSRCRHRCRCCDRPLLSRPDD
Parameter
CMOS/TTLLow-to-HighTransitionTime(Figure2)CMOS/TTLHigh-to-LowTransitionTime(Figure2)ReceiverInputStrobePositionforBit0(Figure9,Figure10)
ReceiverInputStrobePositionforBit1ReceiverInputStrobePositionforBit2ReceiverInputStrobePositionforBit3ReceiverInputStrobePositionforBit4ReceiverInputStrobePositionforBit5ReceiverInputStrobePositionforBit6
ReceiverInputStrobePositionforBit0(Figure9,Figure10)
ReceiverInputStrobePositionforBit1ReceiverInputStrobePositionforBit2ReceiverInputStrobePositionforBit3ReceiverInputStrobePositionforBit4ReceiverInputStrobePositionforBit5ReceiverInputStrobePositionforBit6RxINSkewMargin(Note4)(Figure11)RxCLKOUTPeriod(Figure3)RxCLKOUTHighTime(Figure3)RxCLKOUTLowTime(Figure3)RxOUTSetuptoRxCLKOUT(Figure3)RxOUTHoldtoRxCLKOUT(Figure3)RxCLKOUTHighTime(Figure3)RxCLKOUTLowTime(Figure3)RxOUTSetuptoRxCLKOUT(Figure3)RxOUTHoldtoRxCLKOUT(Figure3)
RxCLKINtoRxCLKOUTDelay@25˚C,VCC=3.3V(Note5)(Figure4)
ReceiverPhaseLockLoopSet(Figure5)ReceiverPowerDownDelay(Figure8)
f=66MHzf=40MHzf=40MHzf=66MHzf=66MHzf=40MHz
1.04.58.111.615.118.822.50.72.95.17.39.511.713.94904001510.010.06.56.05.05.04.54.03.5
T12.211.011.611.67.66.37.36.35.0
7.510150
Min
Typ21.81.45.08.511.915.619.222.91.13.35.57.79.912.114.3
Max552.155.89.1512.616.319.923.61.43.65.88.010.212.414.6
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnspspsnsnsnsnsnsnsnsnsnsnsmsµs
Note4:ReceiverSkewMarginisdefinedasthevaliddatasamplingregionatthereceiverinputs.Thismargintakesintoaccountthetransmitterpulsepositions(minandmax)andthereceiverinputsetupandholdtime(internaldatasamplingwindow-RSPos).ThismarginallowsforLVDSinterconnectskew,inter-symbolinterference(bothdependentontype/lengthofcable),andclockjitter(lessthan250ps).
Note5:Totallatencyforthechannellinkchipsetisafunctionofclockperiodandgatedelaysthroughthetransmitter(TCCD)andreceiver(RCCD).Thetotallatencyforthe215/285transmitterand216A/286Areceiveris:(T+TCCD)+(2*T+RCCD),whereT=Clockperiod.
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DS90CR286A/DS90CR216AACTimingDiagrams
10087302
FIGURE1.“WorstCase”TestPattern
10087304
FIGURE2.DS90CR286A/DS90CR216A(Receiver)CMOS/TTLOutputLoadandTransitionTimes
10087305
FIGURE3.DS90CR286A/DS90CR216A(Receiver)Setup/HoldandHigh/LowTimes
10087306
FIGURE4.DS90CR286A/DS90CR216A(Receiver)ClockIntoClockOutDelay
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DS90CR286A/DS90CR216AACTimingDiagrams
(Continued)
10087307
FIGURE5.DS90CR286A/DS90CR216A(Receiver)PhaseLockLoopSetTime
10087309
FIGURE6.28ParallelTTLDataInputsMappedtoLVDSOutputs-DS90CR286A
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DS90CR286A/DS90CR216AACTimingDiagrams
(Continued)
10087310
FIGURE7.21ParallelTTLDataInputsMappedtoLVDSOutputs-DS90CR216A
10087308
FIGURE8.DS90CR286A/DS90CR216A(Receiver)PowerDownDelay
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DS90CR286A/DS90CR216AACTimingDiagrams
(Continued)
10087325
FIGURE9.DS90CR286A(Receiver)LVDSInputStrobePosition
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DS90CR286A/DS90CR216AACTimingDiagrams
(Continued)
10087326
FIGURE10.DS90CR216A(Receiver)LVDSInputStrobePosition
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DS90CR286A/DS90CR216AACTimingDiagrams
(Continued)
10087311
C—SetupandHoldTime(Internaldatasamplingwindow)definedbyRspos(receiverinputstrobeposition)minandmaxTppos—Transmitteroutputpulseposition(minandmax)
RSKM=CableSkew(type,length)+SourceClockJitter(cycletocycle)(Note6)+ISI(Inter-symbolinterference)(Note7)CableSkew—typically10ps–40psperfoot,mediadependentNote6:Cycle-to-cyclejitterislessthanTBDpsat66MHz.Note7:ISIisdependentoninterconnectlength;maybezero.
FIGURE11.ReceiverLVDSInputSkewMargin
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DS90CR286A/DS90CR216ADS90CR286APinDescription—MTD56Package—28-BitChannelLinkReceiver
PinNameRxIN+RxIN−RxOUTRxCLKIN+RxCLKIN−RxCLKOUTPWRDOWNVCCGNDPLLVCCPLLGNDLVDSVCCLVDSGND
I/OIIOIIOIIIIIII
No.44281111451213
Description
PositiveLVDSdifferentiaIdatainputs.NegativeLVDSdifferentialdatainputs.TTLleveldataoutputs.
PositiveLVDSdifferentialclockinput.NegativeLVDSdifferentialclockinput.
TTLIevelclockoutput.Therisingedgeactsasdatastrobe.
TTLlevelinput.Whenasserted(lowinput)thereceiveroutputsarelow.PowersupplypinsforTTLoutputs.GroundpinsforTTLoutputs.PowersupplyforPLL.GroundpinforPLL.
PowersupplypinforLVDSinputs.GroundpinsforLVDSinputs.
DS90CR216APinDescription—MTD48Package—21-BitChannelLinkReceiver
PinNameRxIN+RxIN−RxOUTRxCLKIN+RxCLKIN−RxCLKOUTPWRDOWNVCCGNDPLLVCCPLLGNDLVDSVCCLVDSGND
I/OIIOIIOIIIIIII
No.33211111451213
Description
PositiveLVDSdifferentiaIdatainputs.(Note8)NegativeLVDSdifferentialdatainputs.(Note8)TTLleveldataoutputs.
PositiveLVDSdifferentialclockinput.NegativeLVDSdifferentialclockinput.
TTLIevelclockoutput.Therisingedgeactsasdatastrobe.
TTLlevelinput.Whenasserted(lowinput)thereceiveroutputsarelow.PowersupplypinsforTTLoutputs.GroundpinsforTTLoutputs.PowersupplyforPLL.GroundpinforPLL.
PowersupplypinforLVDSinputs.GroundpinsforLVDSinputs.
Note8:Thesereceivershaveinputfailsafebiascircuitrytoguaranteeastablereceiveroutputforfloatingorterminatedreceiverinputs.UndertheseconditionsreceiverinputswillbeinaHIGHstate.Ifaclocksignalispresent,outputswillallbeHIGH;iftheclockinputisalsofloating/terminatedoutputswillremaininthelastvalidstate.Afloating/terminatedclockinputwillresultinaLOWclockoutput.
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DS90CR286A/DS90CR216APinDiagramforTSSOPPackages
DS90CR286AMTD
DS90CR216AMTD
10087313
10087323
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DS90CR286A/DS90CR216APhysicalDimensions
unlessotherwisenoted
inches(millimeters)
56-LeadMoldedThinShrinkSmallOutlinePackage,JEDEC
DimensionsshowninmillimetersonlyOrderNumberDS90CR286AMTDNSPackageNumberMTD56
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DS90CR286A/DS90CR216A+3.3VRisingEdgeDataStrobeLVDSReceiver28-BitChannelLink—66MHz,+3.3VRisingEdgeDataStrobeLVDSReceiver21-BitChannelLink—66MHzPhysicalDimensions
inches(millimeters)unlessotherwisenoted(Continued)
48-LeadMoldedThinShrinkSmallOutlinePackage,JEDEC
DimensionsshowninmillimetersonlyOrderNumberDS90CR216AMTDNSPackageNumberMTD48
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