Methods of forming vertical transistor structures

专利名称：Methods of forming vertical transistor

structures

发明人：H. Montgomery Manning,Kunal R.

Parekh,Cem Basceri,Gurtej S. Sandhu

申请号：US11486512申请日：20060713公开号：US07846798B2公开日：20101207

专利附图：

摘要：The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor

structure. The invention also includes methods in which an angled implant is utilized toimplant dopant beneath the gateline of a vertical transistor structure. Vertical transistorstructures formed in accordance with methodology of the present invention can beincorporated into various types of integrated circuitry, including, for example, DRAMarrays.

申请人：H. Montgomery Manning,Kunal R. Parekh,Cem Basceri,Gurtej S. Sandhu

地址：Eagle ID US,Boise ID US,Reston VA US,Boise ID US

国籍：US,US,US,US

代理机构：Wells St. John, P.S.

更多信息请下载全文后查看