Adjustable delay circuit

专利名称：Adjustable delay circuit发明人：Klaas Van Zalinge申请号：US09/124817申请日：19980729公开号：US06124746A公开日：20000926

摘要：An adjustable delay circuit, for a logic input signal, comprises circuitry forcharging a capacitance at a first constant current when the logic signal switches to a firstlogic state; circuitry for discharging the capacitance at a second constant current whenthe logic signal switches to the second logic state; circuitry for stopping charging anddischarging of the capacitance between the moment when the voltage across thecapacitance reaches a high threshold or a low threshold and a subsequent switching ofthe logic signal; and a first comparator connected to switch the state of an output signalwhen the voltage across the capacitance crosses a third threshold included between thefirst and second thresholds.

申请人：STMICROELECTRONICS S.A.

代理机构：Wolf, Greenfield & Sacks, P

代理人：James H. Morris,Theodore E. Galanthay

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