Error correction circuit

专利名称：Error correction circuit

发明人：Nagumo, Masahide c/o Patent Div., Toshiba

Corp.,Kojima, Tadashi c/o Patent Div.,Toshiba Corp.,Inagawa, Jun c/o Patent Div.,Toshiba Corp.

申请号：EP84110573.7申请日：19840905公开号：EP0136587B1公开日：19910417

摘要：An error correction circuit for detecting and correcting a plurality of errors incodewords made up of k data and n - k inspection symbols In the playback data from arecorded medium each symbol made up of m binary bits of information using a Reed-Solomon code for error detection and correction so that the error location polynominala(x) = x8 + σ1xe-1 + ... + σe where e is the number of errors and the coefficients σ1 to σeof the error location polynominal a(x) are related to the error syndromes Si generatedby the error correction circuit by the equationwhere the syndromes Si+e to Si are fieldelements α' of the Galois field GF(2m). The error correction circuit includes: (a) means (12)for generating syndromes S0, S,, S2 and S3 from the codewords; (b) means (17) foreffecting the following three calculations on the basis of the syndromes S0, S1, S2 and S3generated by the syndrome generating meanswhere r3, r2 and r, represent the values ofthe respective calculations; (c) means (23) for judging whether the condition r3 ≠ 0 or r3 =0; (d) a first processing means (17, 25 - 32) for finding error locations by determining theroots of the following equation as the error location polynominal, when the conditions r3

≠ 0 is confirmed in the judging meanswhere x represents the error locations; and (e) asecond processing means (17, 25-32) for finding error location by determining root of thefollowing equation as the error location polynominal, when the condition r3 = 0 isconfirmed in the judging means under the condition of r2 = 0

申请人：KABUSHIKI KAISHA TOSHIBA

地址：72, HORIKAWA-CHO SAIWAI-KU; KAWASAKI-SHI KANAGAWA-KEN 210

代理机构：Blumbach Weser Bergen Kramer

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