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CDCP1803SCAS727E–NOVEMBER2003–REVISEDJANUARY2007
1:3LVPECLCLOCKBUFFERWITHPROGRAMMABLEDIVIDER
FEATURES
••••••••••
DistributesOneDifferentialClockInputtoThreeLVPECLDifferentialClockOutputsProgrammableOutputDividerforTwoLVPECLOutputs
Low-OutputSkew15ps(Typical)VCCRange3V–3.6V
SignalingRateUpto800-MHzLVPECLDifferentialInputStageforWideCommon-ModeRange
ProvidesVBBBiasVoltageOutputforSingle-EndedInputSignals
ReceiverInputThreshold±75mV
24-TerminalQFNPackage(4mm×4mm)AcceptsAnyDifferentialSignaling:LVDS,HSTL,CML,VML,SSTL-2,andSingle-Ended:LVTTL/LVCMOS
RGE PACKAGE(TOP VIEW)
VDD0VDD0S2Y0Y0ENVDDPECLININVDDPECLVBB1234562423222120191817S1S0VDD1Y1Y1VDD1VSS
VSS(1)16151478913101112VSSVDD2(1) Thermal pad must be connected to V.
SS
VDD2NCY2Y2P0024-02
DESCRIPTION
TheCDCP1803clockdriverdistributesonepairofdifferentialclockinputstothreepairsofLVPECLdifferentialclockoutputsY[2:0]andY[2:0]withminimumskewforclockdistribution.TheCDCP1803isspecificallydesignedfordriving50-Ωtransmissionlines.
TheCDCP1803hasthreecontrolterminals,S0,S1,andS2,toselectdifferentoutputmodesettings;seeTable1fordetails.TheCDCP1803ischaracterizedforoperationfrom–40°Cto85°C.Foruseinsingle-endeddriverapplications,theCDCP1803alsoprovidesaVBBoutputterminalthatcanbedirectlyconnectedtotheunusedinputasacommon-modevoltagereference.
S2RTH PACKAGE(TOP VIEW)
VDD0VDD020Y0Y02124232219S1EN
VDDPECL
ININVDDPECL
VBB
1234561012117891817S0VDD1Y1Y1VDD1VSSVSS(1)16151413VSSVDD2(1) Thermal pad must be connected to V.
SS
VDD2NCY2Y2P0025-02
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
Copyright©2003–2007,TexasInstrumentsIncorporated
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CDCP1803SCAS727E–NOVEMBER2003–REVISEDJANUARY2007
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FUNCTIONALBLOCKDIAGRAM
IN
LVPECLINY0Y0Y1
LVPECLDiv 1Div 2Div 4Div 8Div 16LVPECLY2BiasGeneratorVDD − 1.3 V(Imax < 1.5 mA)Y1Y2
VBB
ControlS1S0
S2EN
B0059-02
2
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CDCP1803SCAS727E–NOVEMBER2003–REVISEDJANUARY2007
TERMINALFUNCTIONS
TERMINALNAMEENNO.1I/OI(with60-kΩpullup)DESCRIPTIONENABLE:Enablesordisablesalloutputssimultaneously.EN=1:outputsonaccordingtoS[2:0]settingsEN=0:outputsY[2:0]off(highimpedance)SeeTable1fordetails.Differentialinputclock.Inputstageissensitiveandhasawidecommon-moderange.Therefore,almostanytypeofdifferentialsignalcandrivethisinput(LVPECL,LVDS,CML,HSTL).Becausetheinputishigh-impedance,itisrecommendedtoterminatethePCBtransmissionlinebeforetheinput(e.g.,with100Ωacrossinput).Inputcanalsobedrivenbyasingle-endedsignalifthecomplementaryinputistiedtoVBB.Amore-advancedschemeforsingle-endedsignalsisgivenintheApplicationInformationsectionneartheendofthisdocument.TheinputsemployanESDstructureprotectingtheinputsincaseofaninputvoltageexceedingtherailsbymorethan~0.7V.ReversebiasingoftheICthroughtheseinputsispossibleandmustbepreventedbylimitingtheinputvoltage o//:ptth CDCP1803SCAS727E–NOVEMBER2003–REVISEDJANUARY2007 www.ti.com CONTROLTERMINALSETTINGS TheCDCP1803hasthreecontrolterminals(S0,S1,andS2)andanenableterminal(EN)toselectdifferentoutputmodesettings. Setting for Mode 20:EN = 1S2 = 1S1 = 0S0 = 1 CDCP1803RS2 = OpenENS2REN = OpenRS1 = 0 ΩS1RS0 = OpenS0S0084-02Figure1.ControlTerminalSettingforExample 4 SubmitDocumentationFeedback o//:ptth www.ti.com CDCP1803SCAS727E–NOVEMBER2003–REVISEDJANUARY2007 Table1.SelectionModeTable LVPECL(1)MODE0123456789101112131415161718192021222324252627282930RsvRsv(1) EN011111111111111111111111111VDD/2VDD/2VDD/2VDD/2VDD/2VDD/2S2x00000000VDD/2VDD/2VDD/2VDD/2VDD/2VDD/2VDD/2VDD/2VDD/2111111111000011S1x000VDD/2VDD/2VDD/211000VDD/2VDD/2VDD/2111000VDD/2VDD/2VDD/2111000VDD/2VDD/21S0x0VDD/210VDD/21010VDD/210VDD/210VDD/210VDD/210VDD/210VDD/210VDD/21010÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1÷1ReservedN/AY0Y1Off(high-z)÷1Off(high-z)÷1÷2÷4÷8Off(high-z)÷2÷4÷8Off(high-z)÷1÷2÷4÷8Off(high-z)÷1÷2÷4÷8Off(high-z)÷1÷2÷4÷8Off(high-z)÷1÷2÷4÷8ReservedLow÷1Off(high-z)Off(high-z)Off(high-z)Off(high-z)Off(high-z)÷1÷1÷1÷1÷2÷2÷2÷2÷2÷4÷4÷4÷4÷4÷8÷8÷8÷8÷8÷16÷16÷16÷16÷16ReservedLowY2TheLVPECLoutputsareopen-emitterstages.Thus,iftheunusedLVPECLoutputsY0,Y1,orY2areleftunconnected,thenthecurrentconsumptionisminimizedandnoiseimpacttoremainingoutputsisneglectable.Also,eachoutputcanbeindividuallydisabledbyconnectingthecorrespondingVDDinputtoGND. SubmitDocumentationFeedback 5 o//:ptth CDCP1803SCAS727E–NOVEMBER2003–REVISEDJANUARY2007 www.ti.com ABSOLUTEMAXIMUMRATINGS overoperatingfree-airtemperature(unlessotherwisenoted)(1) VDDVIVO SupplyvoltageInputvoltageOutputvoltage Differentialshort-circuitcurrent,Yn,Yn,IOSD Electrostaticdischarge(HBM1.5kΩ,100pF),ESD Moisturelevel24-terminalQFNpackage(solderreflowtemperatureof235°C)MSL TstgTJ(1) Storagetemperature Maximumjunctiontemperature –0.3Vto3.8V–0.2Vto(VDD+0.2V)–0.2Vto(VDD+0.2V) Continuous>2000V 2 –65°Cto150°C 125°C Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. RECOMMENDEDOPERATINGCONDITIONS MIN VDDTA Supplyvoltage Operatingfree-airtemperature 3–40 TYP3.3 MAX3.685 UNITV°C ELECTRICALCHARACTERISTICS overoperatingfree-airtemperaturerange(unlessotherwisenoted) LVPECLINPUTIN,INPARAMETER fclkVCMVINIINRINCI(1)(2) Inputfrequency High-levelinputcommonmode InputvoltageswingbetweenINandIN(1)InputvoltageswingbetweenINandIN(2)InputcurrentInputimpedance InputcapacitanceatIN,INIsrequiredtomaintainacspecificationsIsrequiredtomaintaindevicefunctionality VI=VDDor0V 300 1 TESTCONDITIONS MIN01500125 TYP MAX800VDD–0.3 13001300±10 UNITMHzVmVµAkΩpF 6 SubmitDocumentationFeedback o//:ptth www.ti.com CDCP1803SCAS727E–NOVEMBER2003–REVISEDJANUARY2007 ELECTRICALCHARACTERISTICS(continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) LVPECLOUTPUTDRIVERY[2:0],Y[2:0]PARAMETERfclkVOHVOLVOIOZLIOZHtr/tftskpecl(o)tDutytsk(pp)COLOAD(1) Outputfrequency,seeFigure3.High-leveloutputvoltageLow-leveloutputvoltageOutputvoltageswingbetweenYandY,seeFigure3.Output3-statecurrentRiseandfalltimesOutputskewbetweenanyLVPECLoutputY[2:0]andY[2:0]Outputduty-cycledistortion(1)Part-to-partskewOutputcapacitanceExpectedoutputloadTerminationwith50ΩtoVDD–2VTerminationwith50ΩtoVDD–2VTerminationwith50ΩtoVDD–2VVDD=3.6V,VO=0VVDD=3.6V,VO=VDD–0.8V20%to80%ofVOUTPP,seeFigure7.SeeNoteAinFigure6.Crossingpoint-to-crossingpointdistortionAnyY,seeNoteBinFigure6.VO=VDDorGND–505015020015TESTCONDITIONSMIN0VDD–1.18VDD–1.985005103503050TYPMAX800VDD–0.81VDD–1.55UNITMHzVVmVµApspspspspFΩForan800-MHzsignal,the50-pserrorwouldresultinadutycycledistortionof±4%whendrivenbyanidealclockinputsignal. LVPECLINPUT-TO-LVPECLOUTPUTPARAMETERS PARAMETERtpd(lh)tpd(hl)tsk(p)Propagationdelay,risingedgePropagationdelay,fallingedgeLVPECLpulseskewTESTCONDITIONSVOXtoVOXVOXtoVOXVOXtoVOX,seeNoteCinFigure6.MIN320320TYPMAX600600100UNITpspspsJITTERCHARACTERISTICS PARAMETERJITTERCHARACTERISTICS12kHzto20MHz,fout=250MHzto800MHz,divide-by-1mode50kHzto40MHz,fout=250MHzto800MHz,divide-by-1mode0.15psrms0.25TESTCONDITIONSMINTYPMAXUNITtjitterLVPECLAdditivephasejitterfrominputtoLVPECLoutputY[2:0],seeFigure2.SubmitDocumentationFeedback 7 o//:ptth CDCP1803SCAS727E–NOVEMBER2003–REVISEDJANUARY2007 www.ti.com ADDITIVEPHASENOISE vs FREQUENCYOFFSETFROMCARRIER–LVPECL −110−115Additive Phase Noise − dBc/Hz−120−125−130−135−140−145−150−155−16010 100 1k 10k 100k 1M 10M 100M G001 LVPECLOUTPUTSWING vs FREQUENCY 0.90 VDD = 3.3 VTA = 25°Cf = 622 MHz÷1 ModeLVPECL Output Swing − V0.850.800.750.700.650.600.550.500.450.40 0.1 VDD = 3.6 VVDD = 3 VVDD = 3.3 VTA = 25°CLoad = 50 Ω to VDD − 2 V0.3 0.5 0.7 0.9 1.1 1.3 1.5 G002 f − Frequency Offset From Carrier − Hzf − Frequency − GHz Figure2.Figure3. SUPPLYCURRENTELECTRICALCHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER Fullload Supplycurrent IDD Noload SupplycurrentsavingperLVPECLoutputstagedisabled,noload IDDZ Supplycurrent,3-state TESTCONDITIONS Alloutputsenabledandterminatedwith50Ωto VDD–2VonLVPECLoutputs,f=800MHzforLVPECLoutputs,VDD=3.3V Outputsenabled,nooutputload,f=800MHzforLVPECLoutputs,VDD=3.6V f=800MHzforLVPECLoutput,VDD=3.3VAlloutputsinhigh-impedancestatebycontrollogic,f=0Hz,VDD=3.6V 10 0.5 mA MIN TYPMAX140 90 mAUNIT 8 SubmitDocumentationFeedback o//:ptth www.ti.com CDCP1803SCAS727E–NOVEMBER2003–REVISEDJANUARY2007 SUPPLYCURRENT vs FREQUENCY 150 VDD = 3.3 V,TA = 255C,50 W to VDD −2 V for LVPECLIDD− Supply Current − mA145 3 LVPECL Outputs(P1) Running140 135 130100300500700900110013001500G003 f − Frequency − MHz Figure4. PACKAGETHERMALRESISTANCE PARAMETER RθJA-1RθJA-2 QFN-24packagethermalresistance(1)QFN-24packagethermalresistancewiththermalviasinPCB(1) TESTCONDITIONS 4-layerJEDECtestboard(JESD51-7),airflow=0ft/min 4-layerJEDECtestboard(JESD51-7)withfourthermalviasof22-mildiametereach,airflow=0ft/min MIN TYP106.655.4 MAX UNIT°C/W°C/W (1) ItisrecommendedtoprovidefourthermalviastoconnectthethermalpadofthepackageeffectivelywiththePCBandensureagoodheatsink. Example: Calculationofthejunction-leadtemperaturewitha4-layerJEDECtestboardusingfourthermalvias:TChassis=85°C(temperatureofthechassis) Peffective=Imax×Vmax=90mA×3.6V=324mW(maxpowerconsumptioninsidethepackage)θTJunction=θJA-2×Peffective=55.45°C/W×324mW=17.97°C TJunction=θTJunction+TChassis=17.97°C+85°C=103°C(themaximumjunctiontemperatureofTdie-max=125°Cisnotviolated) SubmitDocumentationFeedback 9 o//:ptth CDCP1803SCAS727E–NOVEMBER2003–REVISEDJANUARY2007 www.ti.com CONTROLINPUTCHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange PARAMETER tsutht(disable) Setuptime,S0,S1,S2,andENterminalsbeforeclockINHoldtime,S0,S1,S2,andENterminalsafterclockINTimebetweenlatchingtheENlowtransitionandwhenalloutputsaredisabled(howmuchtimeisrequireduntiltheoutputsturnoff) TimebetweenlatchingtheENlow-to-hightransitionandwhenoutputsareenabledbasedoncontrolsettings(howmuchtimepassesbeforetheoutputscarryvalidsignals)InternalpullupresistoronS[2:0]andENinput Three-levelinputhigh,S0,S1,S2,andENterminals(1)Three-levellow,S0,S1,S2,andENterminalsInputcurrent,S0,S1,S2,andENterminals VI=VDDVI=GND 38420.9VDD 0.1VDD –585 TESTCONDITIONS MIN250 10TYP MAX UNITnsnsns t(enable)RpullupVIH(H)VIL(L)IIHIIL(1) 160 78 µskΩVVµAµA LeavingthisterminalfloatingautomaticallypullsthelogiclevelhightoVDDthroughaninternalpullupresistorof60kΩ. BIASVOLTAGEVBB overoperatingfree-airtemperaturerange PARAMETER VBB Outputreferencevoltage TESTCONDITIONS VDD=3V–3.6V,IBB=–0.2mA MINVDD–1.4 TYP MAXVDD–1.2 UNITV OUTPUTREFERENCEVOLTAGE(VBB) vsLOAD 4.0 VDD = 3.3 V3.5VBB − Output Reference Voltage − V3.02.52.01.51.00.50.0−5 0 5 10 15 20 25 30 35 G004 I − Load − mA Figure5. 10 SubmitDocumentationFeedback 分销商库存信息: TI CDCP1803RGETCDCP1803RGETG4 CDCP1803RGERCDCP1803RTHT CDCP1803RGERG4CDCP1803RTHR 因篇幅问题不能全部显示，请点此查看更多更全内容