专利名称：System and method for executing image
computation associated with a target circuit
发明人：Jawahar Jain,Subramanian K. Iyer,Amit
Narayan,Debashis Sahoo,Christian Stangier
申请号：US10454207申请日：20030604公开号：US07032197B2公开日：20060418
专利附图：
摘要：A method for verifying a property associated with a target circuit is providedthat includes receiving information associated with a target circuit, the information
identifying a property within the target circuit to be verified. One or more operations maybe executed in order to generate a set of transition relations for performing areachability analysis associated with the target circuit. An image associated with thetarget circuit may be partitioned into a plurality of leaves that may each represent asubset of a final image to be generated by a partitioned ordered binary decision diagram(POBDD) data structure. An analysis may be computed of one or more of the leaves usinga selected one or both of conjunction and quantification operations separately.
申请人：Jawahar Jain,Subramanian K. Iyer,Amit Narayan,Debashis Sahoo,ChristianStangier
地址：Santa Clara CA US,Austin TX US,Redwood City CA US,Stanford CA US,Los AltosCA US
国籍：US,US,US,US,US
代理机构：Baker Botts L.L.P.
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