专利名称：Integrated structure comprising a patterned
feature substantially of single grainpolysilicon
发明人：Giuseppe Queirolo,Giovanni Ferroni申请号：US10247177申请日：20020919
公开号：US20030017666A1公开日：20030123
摘要：The electrical performance of a dielectric film for capacitive coupling in anintegrated structure is enhanced by forming the polycrystalline electrically conductivelayer coupled with the dielectric film substantially unigranular over the coupling area,commonly to be defined by patterning the stacked dielectric and conductive layers. Theprocess forms a polycrystalline silicon film having exceptionally large grains of a size onthe same order of magnitude as the dimensions of the patterned details. Theseexceptionally large grains are obtained by preventing the formation of “precursornuclei” of subsequent grain formation and growth at the deposition interface with thedielectric that are apparently formed during the first instants of silicon CVD depositionand by successively growing the crystallites at a sufficiently low annealing temperature.
申请人：SGS-THOMSON MICROELECTRONICS S.R.L.
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