专利名称:PARALLEL PROCESSING OF NETWORK
PACKETS
发明人:BREBNER, Gordon, J.申请号:EP12725199.9申请日:20120517公开号:EP2777230B1公开日:20150729
摘要:A packet processing circuit includes a plurality of header extraction circuits (208-214), and a scheduling circuit (206) coupled to the plurality of header extraction circuits.The scheduling circuit is configured to receive one or more requests to extract headerdata of a respective packet from a data bus (202) having a plurality of data lanes (302). Inresponse to each request, the scheduling circuit determines a first subset of the pluralityof data lanes that contain the respective header specified by the request (304), andassigns a respective one of the plurality of header extraction circuits to extract respectiveheader data from the first subset of the plurality of data lanes (306).
申请人:XILINX INC
地址:US
国籍:US
代理机构:Naismith, Robert Stewart
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