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AT24C256

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Features

•Low Voltage and Standard Voltage Operation

–5.0 (VCC = 4.5V to 5.5V)–2.7 (VCC = 2.7V to 5.5V)–1.8 (V•CC = 1.8V to 3.6V)

Internally Organized 16,384 x 8 and 32,768 x 8•2-Wire Serial Interface

•Schmitt Trigger, Filtered Inputs for Noise Suppression•Bidirectional Data Transfer Protocol

•1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility•Write Protect Pin for Hardware and Software Data Protection•-Byte Page Write Mode (Partial Page Writes Allowed)•Self-Timed Write Cycle (5 ms typical)•

High Reliability

–Endurance: 100,000 Write Cycles –Data Retention: 40 Years–ESD Protection: > 4000V

•Automotive Grade and Extended Temperature Devices Available•

8-Pin JEDEC PDIP, 8-Pin JEDEC and EIAJ SOIC, 14-Pin TSSOP, and 8-Pin Leadless Array Packages

Description

The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable andprogrammable read only memory (EEPROM) organized as 16,384/32,768 words of 8bits each. The device’s cascadable feature allows up to 4 devices to share a common2-wire bus. The device is optimized for use in many industrial and commercial applica-tions where low power and low voltage operation are essential. The devices are avail-able in space-saving 8-pin JEDEC PDIP, 8-pin EIAJ, 8-pin JEDEC SOIC, 14-pinTSSOP, and 8-pin LAP packages. In addition, the entire family is available in 5.0V(4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

Pin Configurations

8-Pin PDIP

Pin NameFunctionA18VCC0 to A1Address InputsA0A127WPSDASerial DataNC36SCLGND45SDASCLSerial Clock InputWPWrite ProtectNC

No Connect

8-Pin SOIC

A018VCC14-Pin TSSOP

A127WPNC36SCLA0114VCCGND45SDAA1213WPNC312NCNC411NC8-Pin Leadless Array

NC510NCNC69SCLVCC81A0GND78SDAWP72A1SCL63NCSDAGNDBottom View

2-Wire Serial EEPROMs128K (16,384 x 8)256K (32,768 x 8)AT24C128AT24C256Rev. 0670C–08/981

Absolute Maximum Ratings*

Operating Temperature..................................-55°C to +125°CStorage Temperature.....................................-65°C to +150°CVoltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0VMaximum Operating Voltage...........................................6.25VDC Output Current........................................................5.0 mA

*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Block Diagram

Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positiveedge clock data into each EEPROM device and negativeedge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional forserial data transfer. This pin is open-drain driven and maybe wire-ORed with any number of other open-drain or opencollector devices.

DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0pins are device address inputs that are hardwired or left notconnected for hardware compatibility with AT24C32/.When the pins are hardwired, as many as four 128K/256Kdevices may be addressed on a single bus system (deviceaddressing is discussed in detail under the DeviceAddressing section). When the pins are not hardwired, thedefault A1 and A0 are zero.2

WRITE PROTECT (WP): The write protect input, when tiedto GND, allows normal write operations. When WP is tiedhigh to VCC, all write operations to the memory are inhib-ited. If left unconnected, WP is internally pulled down toGND. Switching WP to VCC prior to a write operation cre-ates a software write protect function.

Memory Organization

AT24C128/256, 128K/256K SERIAL EEPROM: The128K/256K is internally organized as 256/512 pages of -bytes each. Random word addressing requires a 14/15-bitdata word address.

AT24C128/256

Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.

SymbolCI/OCINNote:

Test Condition

Input/Output Capacitance (SDA)Input Capacitance (A0, A1, SCL)

This parameter is characterized and is not 100% tested.

Max86

UnitspFpF

ConditionsVI/O = 0VVIN = 0V

DC Characteristics

Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,VCC = +1.8V to +5.5V (unless otherwise noted).

SymbolVCC1VCC2VCC3ICC1ICC2ISB1

ParameterSupply VoltageSupply VoltageSupply VoltageSupply CurrentSupply CurrentStandby Current(1.8V option)Standby Current(2.7V option)Standby Current(5.0V option)

Input Leakage CurrentOutput Leakage CurrentInput Low Level(Note:)Input High Level(Note:)Output Low LevelOutput Low Level

VCC = 3.0VVCC = 1.8V

IOL = 2.1 mAIOL = 0.15 mA

VCC = 5.0VVCC = 5.0VVCC = 1.8VVCC = 3.6VVCC = 2.7VVCC = 5.5VVCC = 4.5 - 5.5V

READ at 400 kHzWRITE at 400 kHzVIN = VCC or VSS

Test Condition

Min1.82.74.5

1.02.0Typ

Max3.65.55.52.03.00.22.00.56.06.0

0.100.05

-0.6VCC x 0.7

3.03.0VCC x 0.3VCC + 0.50.40.2

µAµAµAVVVVµAUnitsVVVmAmAµA

ISB2ISB3ILIILOVILVIHVOL2VOL1Note:

VIN = VCC or VSSVIN = VCC or VSSVIN = VCC or VSSVOUT = VCC or VSS

VIL min and VIH max are reference only and are not tested

AC Characteristics

Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-erwise noted). Test conditions are listed in Note 2.

1.8-volt

SymbolfSCLtLOWtHIGHtAAtBUFtHD.STAtSU.STAtHD.DATtSU.DATtRtFtSU.STOtDHtWR

Endurance(1)Notes:

Parameter

Clock Frequency, SCLClock Pulse Width LowClock Pulse Width HighClock Low to Data Out Valid

Time the bus must be free before a new transmission can start(1)Start Hold TimeStart Set-up TimeData In Hold TimeData In Set-up TimeInputs Rise Time(1)Inputs Fall Time(1)Stop Set-up TimeData Out Hold TimeWrite Cycle Time5.0V, 25°C, Page Mode

100K4.7100

100K

4.74.00.14.74.04.70200

1.0300

0.650

100K

4.5

Min

Max100

1.31.00.051.30.60.60100

0.3300

0.2550

0.9

2.7-voltMin

Max400

0.60.40.050.50.250.250100

0.31000.555.0-voltMin

Max1000

UnitskHzµsµsµsµsµsµsµsnsµsnsµsnsmsWrite Cycles

1.This parameter is characterized and is not 100% tested.2.AC measurement conditions:

RL (connects to VCC): 1.3KΩ (2.7V, 5V), 10KΩ (1.8V)Input pulse voltages: 0.3VCC to 0.7VCCInput rise and fall times: ≤50ns

Input and output timing reference voltages: 0.5VCC

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is nor-mally pulled high with an external device. Data on the SDApin may change only during SCL low time periods (refer toData Validity timing diagram). Data changes during SCLhigh periods will indicate a start or stop condition as definedbelow.

START CONDITION: A high-to-low transition of SDA withSCL high is a start condition which must precede any othercommand (refer to Start and Stop Definition timing dia-gram).

STOP CONDITION: A low-to-high transition of SDA withSCL high is a stop condition. After a read sequence, thestop command will place the EEPROM in a standby powermode (refer to Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are seri-ally transmitted to and from the EEPROM in 8-bit words.The EEPROM sends a zero during the ninth clock cycle toacknowledge that it has received each word.

STANDBY MODE: The AT24C128/256 features a lowpower standby mode which is enabled: a) upon power-upand b) after the receipt of the STOP bit and the completionof any internal operations.

MEMORY RESET: After an interruption in protocol, powerloss or system reset, any 2-wire part can be reset by follow-ing these steps: (a) Clock up to 9 cycles, (b) look for SDAhigh in each cycle while SCL is high and then (c) create astart condition as SDA is high.

AT24C128/256

Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

SCLSDA8th BITACKWORD nt(1)WRSTOPSTARTCONDITIONCONDITIONNote:

The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

Data Validity

Start and Stop Definition

Output Acknowledge

AT24C128/256

Device Addressing

The 128K/256K EEPROM requires an 8-bit device addressword following a start condition to enable the chip for a reador write operation (refer to Figure 1). The device addressword consists of a mandatory one, zero sequence for thefirst five most significant bits as shown. This is common toall 2-wire EEPROM devices.

The 128K/256K uses the two device address bits A1, A0 toallow as many as four devices on the same bus. These bitsmust compare to their corresponding hardwired input pins.The A1 and A0 pins use an internal proprietary circuit thatbiases them to a logic low condition if the pins are allowedto float.

The eighth bit of the device address is the read/write opera-tion select bit. A read operation is initiated if this bit is highand a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM willoutput a zero. If a compare is not made, the device willreturn to a standby state.

DATA SECURITY: The AT24C128/256 has a hardwaredata protection scheme that allows the user to write protectthe whole memory when the WP pin is at VCC.

data word address will “roll over” and previous data will beoverwritten. The address “roll over” during write is from thelast byte of the current page to the first byte of the samepage.

ACKNOWLEDGE POLLING: Once the internally-timedwrite cycle has started and the EEPROM inputs are dis-abled, acknowledge polling can be initiated. This involvessending a start condition followed by the device addressword. The read/write bit is representative of the operationdesired. Only if the internal write cycle has completed willthe EEPROM respond with a zero, allowing the read orwrite sequence to continue.

Read Operations

Read operations are initiated the same way as write opera-tions with the exception that the read/write select bit in thedevice address word is set to one. There are three readoperations: current address read, random address readand sequential read.

CURRENT ADDRESS READ: The internal data wordaddress counter maintains the last address accessed dur-ing the last read or write operation, incremented by one.This address stays valid between operations as long as thechip power is maintained. The address “roll over” duringread is from the last byte of the last memory page, to thefirst byte of the first page.

Once the device address with the read/write select bit setto one is clocked in and acknowledged by the EEPROM,the current address data word is serially clocked out. Themicrocontroller does not respond with an input zero butdoes generate a following stop condition (refer to Figure 4).RANDOM READ: A random read requires a “dummy” bytewrite sequence to load in the data word address. Once thedevice address word and data word address are clocked inand acknowledged by the EEPROM, the microcontrollermust generate another start condition. The microcontrollernow initiates a current address read by sending a deviceaddress with the read/write select bit high. The EEPROMacknowledges the device address and serially clocks outthe data word. The microcontroller does not respond with azero but does generate a following stop condition (refer toFigure 5).

SEQUENTIAL READ: Sequential reads are initiated byeither a current address read or a random address read.After the microcontroller receives a data word, it respondswith an acknowledge. As long as the EEPROM receives anacknowledge, it will continue to increment the data wordaddress and serially clock out sequential data words. Whenthe memory address limit is reached, the data wordaddress will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated whenthe microcontroller does not respond with a zero but doesgenerate a following stop condition (refer to Figure 6).

Write Operations

BYTE WRITE: A write operation requires two 8-bit dataword addresses following the device address word andacknowledgment. Upon receipt of this address, theEEPROM will again respond with a zero and then clock inthe first 8-bit data word. Following receipt of the 8-bit dataword, the EEPROM will output a zero. The addressingdevice, such as a microcontroller, then must terminate thewrite sequence with a stop condition. At this time theEEPROM enters an internally-timed write cycle, tWR, to thenonvolatile memory. All inputs are disabled during thiswrite cycle and the EEPROM will not respond until the writeis complete (refer to Figure 2).

PAGE WRITE: The 128K/256K EEPROM is capable of -byte page writes.

A page write is initiated the same way as a byte write, butthe microcontroller does not send a stop condition after thefirst data word is clocked in. Instead, after the EEPROMacknowledges receipt of the first data word, the microcon-troller can transmit up to 63 more data words. TheEEPROM will respond with a zero after each data wordreceived. The microcontroller must terminate the pagewrite sequence with a stop condition (refer to Figure 3).The data word address lower 6 bits are internally incre-mented following the receipt of each data word. The higherdata word address bits are not incremented, retaining thememory page row location. When the word address, inter-nally generated, reaches the page boundary, the followingbyte is placed at the beginning of the same page. If morethan data words are transmitted to the EEPROM, the

Figure 1. Device Address

Figure 2. Byte Write

Figure 3. Page Write

(* = DON’T CARE bit)

(† = DON’T CARE bit for the 128K)Figure 4. Current Address Read

AT24C128/256

Figure 5. Random Read

(* = DON’T CARE bit)

(† = DON’T CARE bit for the 128K)Figure 6. Sequential Read

AT24C128 Ordering Information

tWR (max)(ms)

ICC (max)(µA)3000

ISB (max)(µA)6.0

fMAX(kHz)1000

Ordering CodeAT24C128-10PCAT24C128N-10SCAT24C128W-10SCAT24C128-10CCAT24C128C1-10CCAT24C128T1-10TCAT24C128-10PIAT24C128N-10SIAT24C128W-10SIAT24C128-10CIAT24C128C1-10CIAT24C128T1-10TIAT24C128-10PC-2.7AT24C128N-10SC-2.7AT24C128W-10SC-2.7AT24C128-10CC-2.7AT24C128C1-10CC-2.7AT24C128T1-10TC-2.7AT24C128-10PI-2.7AT24C128N-10SI-2.7AT24C128W-10SI-2.7AT24C128-10CI-2.7AT24C128C1-10CI-2.7AT24C128T1-10TI-2.7

Package8P38S18S28C8C114T8P38S18S28C8C114T8P38S18S28C8C114T8P38S18S28C8C114T

Operation RangeCommercial(0°C to 70°C)

30006.01000

Industrial(-40°C to 85°C)

1015000.00

Commercial(0°C to 70°C)

15000.00

Industrial(-40°C to 85°C)

Package Type

8C8C18P38S18S214TBlank-2.7-1.8

8-Lead, 0.230\" Wide, Leadless Array Package (LAP)8-Lead, 0.300\" Wide, Leadless Array Package (LAP)8-Lead, 0.300\" Wide, Plastic Dual Inline Package (PDIP)

8-Lead, 0.150\" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)8-Lead, 0.200\" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)14-Lead, 0.170\" Wide, Thin Shrink Small Outline Package (TSSOP)

Options

Standard Operation (4.5V to 5.5V)Low-Voltage (2.7V to 5.5V)Low-Voltage (1.8V to 3.6V)

AT24C128/256

AT24C128 Ordering Information (Continued)

tWR (max)(ms)

ICC (max)(µA)800

ISB (max)(µA)0.2

fMAX(kHz)100

Ordering CodeAT24C128-10PC-1.8AT24C128N-10SC-1.8AT24C128W-10SC-1.8AT24C128-10CC-1.8AT24C128C1-10CC-1.8AT24C128T1-10TC-1.8AT24C128-10PI-1.8AT24C128N-10SI-1.8AT24C128W-10SI-1.8AT24C128-10CI-1.8AT24C128C1-10CI-1.8AT24C128T1-10TI-1.8

Package8P38S18S28C8C114T8P38S18S28C8C114T

Operation RangeCommercial(0°C to 70°C)

8000.2100

Industrial(-40°C to 85°C)

Package Type

8C8C18P38S18S214TBlank-2.7-1.8

8-Lead, 0.230\" Wide, Leadless Array Package (LAP)8-Lead, 0.300\" Wide, Leadless Array Package (LAP)8-Lead, 0.300\" Wide, Plastic Dual Inline Package (PDIP)

Options

Standard Operation (4.5V to 5.5V)Low-Voltage (2.7V to 5.5V)Low-Voltage (1.8V to 3.6V)

AT24C256 Ordering Information

tWR (max)(ms)

ICC (max)(µA)3000

ISB (max)(µA)6.0

fMAX(kHz)1000

Ordering CodeAT24C256-10PCAT24C256N-10SCAT24C256W-10SCAT24C256-10CCAT24C256C1-10CCAT24C256T1-10TCAT24C256-10PIAT24C256N-10SIAT24C256W-10SIAT24C256-10CIAT24C256C1-10CIAT24C256T1-10TIAT24C256-10PC-2.7AT24C256N-10SC-2.7AT24C256W-10SC-2.7AT24C256-10CC-2.7AT24C256C1-10CC-2.7AT24C256T1-10TC-2.7AT24C256-10PI-2.7AT24C256N-10SI-2.7AT24C256W-10SI-2.7AT24C256-10CI-2.7AT24C256C1-10CI-2.7AT24C256T1-10TI-2.7

Package8P38S18S28C8C114T8P38S18S28C8C114T8P38S18S28C8C114T8P38S18S28C8C114T

Operation RangeCommercial(0°C to 70°C)

30006.01000

Industrial(-40°C to 85°C)

1015000.00

Commercial(0°C to 70°C)

15000.00

Industrial(-40°C to 85°C)

Package Type

8C8C18P38S18S214TBlank-2.7-1.8

8-Lead, 0.230\" Wide, Leadless Array Package (LAP)8-Lead, 0.300\" Wide, Leadless Array Package (LAP)8-Lead, 0.300\" Wide, Plastic Dual Inline Package (PDIP)

Options

Standard Operation (4.5V to 5.5V)Low-Voltage (2.7V to 5.5V)Low-Voltage (1.8V to 3.6V)

AT24C128/256

AT24C256 Ordering Information (Continued)

tWR (max)(ms)

ICC (max)(µA)800

ISB (max)(µA)0.2

fMAX(kHz)100

Ordering CodeAT24C256-10PC-1.8AT24C256N-10SC-1.8AT24C256W-10SC-1.8AT24C256-10CC-1.8AT24C256C1-10CC-1.8AT24C256T1-10TC-1.8AT24C256-10PI-1.8AT24C256N-10SI-1.8AT24C256W-10SI-1.8AT24C256-10CI-1.8AT24C256C1-10CI-1.8AT24C256T1-10TI-1.8

Package8P38S18S28C8C114T8P38S18S28C8C114T

Operation RangeCommercial(0°C to 70°C)

8000.2100

Industrial(-40°C to 85°C)

Package Type

8C8C18P38S18S214TBlank-2.7-1.8

8-Lead, 0.230\" Wide, Leadless Array Package (LAP)8-Lead, 0.300\" Wide, Leadless Array Package (LAP)8-Lead, 0.300\" Wide, Plastic Dual Inline Package (PDIP)

Options

Standard Operation (4.5V to 5.5V)Low-Voltage (2.7V to 5.5V)Low-Voltage (1.8V to 3.6V)

AT24C128/256

Packaging Information

8C, 8-Lead, 0.230\" Wide, Leadless Array Package (LAP)Dimensions in Inches and (Millimeters)8C1, 8-Lead, 0.300\" Wide, Leadless Array Package (LAP)Dimensions in Inches and (Millimeters)TOP VIEWSIDEVIEWTOP VIEWSIDEVIEW5.15 (0.203)4.85 (0.191)5.15 (0.203)4.85 (0.191)6.15 (0.242)5.85 (0.230)1.30 (0.051)1.00 (0.039)0.42 (0.017)0.34 (0.013)8.15 (0.321)7.85 (0.309)1.30 (0.051)1.00 (0.039)0.42 (0.017)0.34 (0.013)BOTTOM VIEW871.27 (0.050) TYP650. (0.025) TYP34120.41 (0.016) TYPBOTTOM VIEW871.27 (0.050) TYP650. (0.025) TYP34120.41 (0.016) TYP8P3, 8-Lead, 0.300\" Wide,Plastic Dual Inline Package (PDIP)Dimensions in Inches and (Millimeters)JEDEC STANDARD MS-001 BA.400 (10.16).355 (9.02)PIN1.280 (7.11).240 (6.10).037 (.940).027 (.690)8S1, 8-Lead, 0.150\" Wide,Plastic Gull Wing Small Outline (JEDEC SOIC)Dimensions in Inches and (Millimeters).020 (.508).013 (.330)PIN 1 .157 (3.99).150 (3.81).244 (6.20).228 (5.79).300 (7.62) REF.050 (1.27) BSC.210 (5.33) MAXSEATINGPLANE.150 (3.81).115 (2.92).070 (1.78).045 (1.14).015 (.380) MIN.022 (.559).014 (.356).100 (2.) BSC.196 (4.98).1 (4.80).068 (1.73).053 (1.35).325 (8.26).300 (7.62).012 (.305).008 (.203)0REF15.430 (10.9) MAX.010 (.2).004 (.102)0REF8.050 (1.27).016 (.406).010 (.2).007 (.203)14

Packaging Information

8S2, 8-Lead, 0.200\" Wide,Plastic Gull Wing Small Outline (EIAJ SOIC)Dimensions in Inches and (Millimeters)14T, 14-Lead, 0.170\" Wide, Thin Shrink Small Outline Package (TSSOP)Dimensions in Inches and (Millimeters).020 (.508).012 (.305)INDEX MARKPIN1PIN 1 .213 (5.41).205 (5.21).330 (8.38).300 (7.62)4.50 (.177)4.30 (.169)6.50 (.256)6.25 (.246).050 (1.27) BSC.212 (5.38).203 (5.16).080 (2.03).070 (1.78).650 (.026) BSC5.10 (.201)4.90 (.193)1.20 (.047) MAX.013 (.330).004 (.102)0REF8.035 (.8).020 (.508).010 (.2).007 (.178)0REF80.30 (.012)0.19 (.007)0.15 (.006)0.05 (.002)SEATINGPLANE0.20 (.008)0.09 (.004)0.75 (.030)0.45 (.018)*Controlling dimension: millimeters15

AT24C128/256

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