HDB3码的译码器

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity zv is

port(fb,zb:IN std_logic; zvout:out std_logic); end zv;

architecture bh of zv is

signal M:std_logic_vector(2 downto 0); begin

process(zb,fb) begin

if fb='1' then M<=\"000\"; elsif zb'event and zb='1' then if M<2 then M<=M+1;

end if; end if;

end process;

process(fb,M) begin

if fb='0' then if M<2 then zvout<='0'; else

zvout<=zb; end if; else zvout<='0'; end if;

end process; end bh;

2. -V码检测

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity fv is

port(fb,zb:IN std_logic; fvout:out std_logic); end fv;

architecture hh of fv is

signal N:std_logic_vector(2 downto 0); begin

process(zb,fb) begin

if zb='1' then N<=\"000\"; elsif fb'event and fb='1' then if N<2 then N<=N+1;

end if; end if; end process;

process(zb,N) begin

if zb='0' then if N<2 then fvout<='0'; else

fvout<=fb; end if; else fvout<='0'; end if;

end process; end hh;

3．扣V扣B

library ieee;

use ieee.std_logic_1164.all; entity kvb is

port(clk:in std_logic;

v,datain:in std_logic; decode:out std_logic); end kvb;

architecture behav of kvb is

signal A0,A1,A2,A3:std_logic; begin

process(clk,v) begin

if clk'event and clk='1' then if(v='1') then A0<='0'; A1<='0'; A2<='0'; A3<='0'; decode<=A0;

elsif(V='0') then A3<=datain; A2<=A3; A1<=A2; A0<=A1; decode<=A0; end if; end if;

end process; end behav;