Rev 1.2
RK2906-6 Datasheet
Revision 1.0 Mar. 2012
Rockchips Confidential 1
RK2906-6 Datasheet
Rev 1.2
Date 2012-3-7 Revision 1.0 Revision History
Description Initial Release
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RK2906-6 Datasheet
Rev 1.2
Table of Content
Table of Content ............................................................................................... 3 Figure Index .................................................................................................... 5 Table Index ..................................................................................................... 6 Chapter 1 Introduction .................................................................................... 7 1.1 Features ........................................................................................... 7
1.1.1 Microprocessor .......................................................................... 7
1.1.2 Memory Organization ................................................................. 8 1.1.3 Internal Memory ........................................................................ 8 1.1.4 External Memory or Storage device .............................................. 8 1.1.5 System Component .................................................................... 9 1.1.6 Video CODEC........................................................................... 11 1.1.7 JPEG CODEC ........................................................................... 12 1.1.8 Image Enhancement ................................................................ 13 1.1.9 Graphics Engine ....................................................................... 14 1.1.10 Video IN/OUT .......................................................................... 15 1.1.11 Audio Interface ........................................................................ 16 1.1.12 Connectivity ............................................................................ 17 1.1.13 Others .................................................................................... 18 Block Diagram ................................................................................. 19
1.2
Chapter 2 Package Description ....................................................................... 20 2.1 Ball Map ......................................................................................... 20
2.2 Pin Number Order ............................................................................ 24 2.3 RK2906-6 power/ground IO descriptions ............................................ 29 2.4 2.5
2.3.1 RK2906-6 function IO descriptions ............................................. 33
IO pin name descriptions .................................................................. 43 2.4.1 RK2906-6 IO Type .................................................................... 47 Package information ......................................................................... 49
2.5.1 Dimension .............................................................................. 49
Chapter 3 Electrical Specification .................................................................... 51 3.1 Absolute Maximum Ratings ............................................................... 51
3.2 Recommended Operating Conditions .................................................. 51 3.3 DC Characteristics ........................................................................... 52 3.4 Electrical Characteristics for General IO .............................................. 53 3.5 Electrical Characteristics for PLL ........................................................ 3.6 Electrical Characteristics for SAR-ADC ................................................ 55 3.7 Electrical Characteristics for USB OTG/Host2.0 Interface ....................... 55 3.8 Electrical Characteristics for USB Host1.1 Interface .............................. 56 3.9 Electrical Characteristics for DDR IO ................................................... 56 3.10
Electrical Characteristics for eFuse ................................................ 56
Chapter 4 Hardware Guideline ........................................................................ 57 4.1 Reference design for RK2906-6 oscillator PCB connection ..................... 57
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4.2 Reference design for PLL PCB connection ............................................ 57 4.3 Reference design for USB OTG/Host2.0 connection .............................. 58 4.4 RK2906-6 Power up/down sequence requirement ................................ 58 4.5 RK2906-6 Power on reset descriptions ................................................ 59
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RK2906-6 Datasheet
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Figure Index
Fig. 1-1 RK2906-6 Block Diagram ..................................................................... 19 Fig. 2-1 RK2906-6 Ball Mapping Diagram ........................................................... 23 Fig. 2-2 RK2906-6 TFBGA512 Package Top View ................................................. 49 Fig. 2-3 RK2906-6 TFBGA512 Package Side View ................................................ 49 Fig. 2-4 RK2906-6 TFBGA512 Package Bottom View ............................................ 50 Fig. 2-5 RK2906-6 TFBGA512 Package Dimension ............................................... 50 Fig. 4-1 External reference circuit for 24MHz oscillators ....................................... 57 Fig. 4-2 External reference circuit for PLL .......................................................... 57 Fig. 4-3 RK2906-6 USB OTG/Host2.0 interface reference connection ...................... 58 Fig. 4-4 RK2906-6 reset signals sequence.......................................................... 59
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RK2906-6 Datasheet
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Table Index
Table 2-1 RK2906-6 Pin Number Order Information ............................................. 24 Table 2-2 RK2906-6 Power/Ground IO informations ............................................. 29 Table 2-3 RK2906-6 IO descriptions .................................................................. 33 Table 2-4 RK2906-6 IO function description list .................................................. 43 Table 2-5 RK2906-6 IO Type List ...................................................................... 47 Table 3-1 RK2906-6 absolute maximum ratings .................................................. 51 Table 3-2 RK2906-6 recommended operating conditions ...................................... 51 Table 3-3 RK2906-6 DC Characteristics ............................................................. 52 Table 3-4 RK2906-6 Electrical Characteristics for Digital General IO ....................... 53 Table 3-5 RK2906-6 Electrical Characteristics for PLL ........................................... Table 3-6 RK2906-6 Electrical Characteristics for SAR-ADC ................................... 55 Table 3-7 RK2906-6 Electrical Characteristics for USB OTG/Host2.0 Interface .......... 55 Table 3-8 RK2906-6 Electrical Characteristics for USB Host1.1 Interface ................. 56 Table 3-9 RK2906-6 Electrical Characteristics for DDR IO ..................................... 56 Table 3-10 RK2906-6 Electrical Characteristics for eFuse ...................................... 56
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RK2906-6 Datasheet
Rev 1.2
Chapter 1 Introduction
RK2906-6 is a low power, high performance processor solution for mobile phones, personal mobile internet device and other digital multimedia applications.
RK2906-6 integrates an ARM Cortex-A8 with one NEON coprocessor. Many
embedded powerful hardware accelerators provide optimized hardware performance for high-end application. RK2906-6 supports almost full-format video decoder by
1080p@30fps such as H2, H263, RMVB, MPEG2, MPEG4, VC1, AVS, VP8 etc. Also supports H.2 encoder by 1080P@30fps, high-quality JPEG encoder/decoder and special image preprocessor and postprocessor.
Embedded 2D/3D hardware engine makes RK2906-6 completely compatible with OpenGL ES2.0, OpenGL ES1.1 and OpenVG graphics standards.
RK2906-6 has high-performance external memory interface (DDRIII/DDRII/LPDDR) capable of sustaining demanding memory bandwidths, also provides a complete set of peripheral interface to support very flexible applications as follows:
8 banks, 8bits Async NAND FLASH, LBA NANDN Flash, 8bits sync ONFI NAND Flash, all embedded 24bits HW ECC
1 ranks, 1GB Memory space, 16bits DDRIII,DDRII-800,LPDDR-400 4bits HS-MMC/SD,
24bits high-performance, 3-layers TFT LCD Controller with post-processor,
1920x1080 maximum display size 8bits sensor/CCIR656 interface Two 2ch I2S interface
USB OTG 2.0/USB Host2.0/ USB Host 1.0
4x I2C, 4xUART with hardware flow-control , 2x SPI , PWM
This document will provide guideline on how to use RK2906-6 correctly and efficiently. In them, the chapter 1 and chapter 2 will introduce the features, block diagram, and signal descriptions and system usage of RK2906-6, the chapter 3 through chapter 46 will describe the full function of each module in detail. 1.1
1.1.1
Features
Microprocessor
ARM Cortex-A8 processor is a high-performance, low-power, cached application
processor that provides full virtual memory capabilities Full implementation of the ARM architecture v7-A instruction set superscalar processor featuring technology for enhanced code density and performance
Embedded NEON technology for multimedia and signal processing by executing Advanced SIMD and VFP instruction sets Jazelle RCT Java-acceleration technology for efficient support of ahead-of-time and just-in-time compilation of Java and other byte code language Thumb-2 technology for greater performance, energy efficiency and code density TrustZone technology for secure transactions and DRM 13-stage main integer core pipeline and 10-stage NEON media core pipeline
Dynamic branch prediction with branch target address cache, global history buffer
and 8-entry return stack
MMU and separate instruction and data TLBs of 32 entries each
-bit high-speed AXI interface supporting multiple outstanding transactions
Integrated 32KB L1 instruction cache , 32KB L1 data cache, 512KB L2 Cache with
parity and ECC check
ETM support for non-invasive debug, support JTAG and 8-wire trace interface ARMv7 debug with watchpoint and breakpoint registers and a 32-bit APB slave
interface to a coresight debug system
Four separate power domain to support Internal power switch on/off based on
different application scene(Integer core/ETM&DBG/Neon/L2 Cache)
Maximum frequency can be up to 650MHz@worst case and 1GHz@typical case
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RK2906-6 Datasheet
1.1.2
Memory Organization
Rev 1.2
Internal on-chip memory
10KB Boot Rom
16KB internal SRAM for security and non-security access, detailed size is
programmable
4KB internal SRAM shared with Host slave interface (HIF) 2KB internal SRAM shared with NAND controller
①
External off-chip memory
DDRIII, DDRII-800, 16bits data width, 1 ranks, 1GB(max) address space per
rank
LPDDR-400, 16bits data width, 1 ranks, 1GB(max) address space per rank Async NAND Flash(include LBA NAND), 8 data width, 8 banks Sync DDR NAND Flash, 8bits data width, 8 banks
1.1.3 Internal Memory
Internal Boot Rom
Size : 10KB
Support system boot from the following device :
8bits/16bits Async NAND Flash SPI0 interface
Support system code download by the following interface: USB OTG UART1
Internal SRAM
Size : 16KB
Support security and non-security access Security or non-security space is software programmable , used together with TZMA module
Security space can be 0KB, 4KB, 8KB, 12KB, 16KB continuous size
1.1.4 External Memory or Storage device Dynamic Memory Interface (DDRIII/DDRII/LPDDR) Compatible with JEDEC standard DDRIII/DDRII/LPDDR SDRAM Data rates of up to 800Mbps(400MHz) for DDRII and up to 400Mbps(200MHz) for LPDDR
Support up to 2 ranks (chip selects), maximum 1GB address space per rank 16bits/32bits data width is software programmable 5 host ports with bits AXI bus interface for system access, AXI bus clock asynchronous with DDR clock Programmable timing parameters support DDRIII/DDRII/LPDDR SDRAM from various vendor Advanced command reordering and scheduling to maximize bus utilization Low power modes, such as power-down and self-refresh for DDRII/LPDDR SDRAM; clock stop and deep power-down for LPDDR SDRAM
Programmable ultra-high priority port(port0), typically a CPU port
Compensation for board delays and variable latencies through programmable
pipelines
Embedded dynamic drift detection in the PHY to get dynamic drift compensation
with the controller
Programmable output and ODT impedance with dynamic PVT compensation Support one low-power work mode: power down DDR PHY and most of DDR IO
except two CS and two CKE output signals, make SDRAM still in self-refresh state to prevent data missing.
NAND Flash Interface
Support 8bits async NAND flash, up to 8 banks
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Support 8bits sync DDR NAND flash, up to 8 banks Support LBA NAND flash in async or sync mode 16bit/1KB HW ECC, compatible with 8bit/512B 24bit/1KB HW ECC, compatible with 12bit/512B
For DDR NAND flash, support DLL bypass and 1/4 or 1/8 clock adjust, maximum clock rate is 75MHz
For async NAND flash, support configurable interface timing , maximum data
rate is 16bit/cycle
Embedded two 256x32bits buffers to support ping-pong operation Embedded AHB master interface to do data transfer by DMA method
Also support data transfer by AHB slave interface together with external DMAC1
SD/MMC Interface
Compatible with SD ver2.00, CE-ATA ver1.1, MMC ver4.2
One AHB slave interface to complete data transfer together with external DMAC1 or CPU
Support combined single FIFO(32x32bits) for both transmit and receive operations
Support FIFO over-run and under-run prevention by stopping card clock automatically
Support CRC generation and error detection
Embedded clock frequency division control to provide programmable baud rate Support host pull-up control, card detection and initialization, write protection Support block size from 1 to 65535Bytes
Data bus width is flexible to support 1bit/4bits for SD mode and 1bit/4bits/8bits for MMC mode
1.1.5 System Component
CRU (clock & reset unit)
Support clock gating control for individual components inside RK2906-6 Support soft-reset control for individual components inside RK2906-6 Support flexible clock solution, including clock source, clock MUX, clock frequency division
Four embedded PLLs, source can be from two external 24MHz oscillator input, also support two-level cascaded PLL to meet special clock frequency requirement Up to 1.6GHz clock output for ARM PLL, up to 1.0GHz clock output for another three PLLs
PMU(power management unit) Provide five work modes(slow mode, normal mode, idle mode, stop mode, power-down mode) to save power by different frequency or automatically clock gating control or power domain on/off control Idle mode can be wakeup by any interrupt from every on-chip components or external GPIO
Stop mode and power-down mode can be wakeup by external dedicated IO or 96 different GPIOs or RTC alarm
Provide 9 separately power domains, which can be power up/down by software
based on different application scenes
Timer
Four on-chip 32bits Timers with interrupt-based operation
Provide two operation modes: free-running and user-defined count Support timer work state checkable
timer0 and timer1 are for CPU system domain, timer2 and timer3 are for peri
system domain
support independent fixed clock for timer0 and timer1 from external 24MHz
clock input, asynchronous with APB bus clock
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PWM
Four on-chip PWMs with interrupt-based operation Programmable 4-bit pre-scalar from apb bus clock Embedded 32-bit timer/counter facility
Support single-run or continuous-run PWM mode Support maskable interrupt
Provides reference mode and output various duty-cycle waveform
Provides capture mode and measure the duty-cycle of input waveform
WatchDog
32 bits watchdog counter width
Counter clock is from APB bus clock
Counter counts down from a preset value to 0 to indicate the occurrence of a timeout
WDT can perform two types of operations when timeout occurs: Generate a system reset
First generate an interrupt and if this is not cleared by the service routine by the time a second timeout occurs then generate a system reset Programmable reset pulse length
Totally 16 defined-ranges of main timeout period
Bus Architecture
-bit multi-layer AXI/AHB composite bus architecture Six embedded AXI interconnect
CPU L1 interconnect with two -bits AXI masters and six 32/bits AXI slaves
CPU L2 interconnect with one 32-bits AXI master, 32-bits AXI slave and lots
of 32-bits AHB /APB slaves Peri interconnect with two -bits AXI masters, one -bits AXI slave, one 32-bits AXI slave, two 32-bits AHB masters and lots of 32-bits AHB/APB slaves
Display interconnect with three -bits AXI masters, two 32-bits AHB masters and one -bits AXI slave GPU and VCODEC interconnect also with one -bits AXI master and one -bits AXI slave ,they are point-to-point AXI-lite architecture For each interconnect with AXI/AHB/APB composite bus, clocks for AXI/AHB/APB domains are always synchronous, and different integer ratio is supported for them. For CPU L1/CPU L2/Peri three interconnects, provide GPV registers to be programmed by software to support different application scenes
Interrupt Controller Support 71 interrupt sources input from different components inside RK2906-6
or GPIO
Support 16 software-triggered interrupts
Two AXI slave interfaces for shared distributor and cpu to manage individual
registers with different intention
Input interrupt level is fixed , only high-level sensitive
Two interrupt output (nFIQ and nIRQ) to Cortex-A8, both are low-level sensitive Support different interrupt priority for each interrupt source, and they are
always software-programmable
Support security extension to make some registers only be accessed in system
security mode
DMAC
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support dependent clock for timer2 and timer3 from system, same as APB bus
clock
RK2906-6 Datasheet
Rev 1.2
Micro-code programming based DMA
The specific instruction set provides flexibility for programming DMA transfers Linked list DMA function is supported to complete scatter-gather transfer Support internal instruction cache Embedded DMA manager thread
Support data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory
Signals the occurrence of various DMA events using the interrupt output signals Mapping relationship between each channel and different interrupt outputs is
software-programmable
Two embedded DMA controller , DMAC0 is for CPU system, DMAC1 is for peri
system
DMAC0 features:
6 channels totally
8 hardware request from peripherals 3 interrupt output
Dual APB slave interface for register configure, designated as secure and non-secure
Support trustzone technology and programmable secure state for each DMA channel
DMAC1 features:
7 channels totally
20 hardware request from peripherals 4 interrupt output
Not support trustzone technology
Security system
Support trustzone technology for the following components inside RK2906-6 Cortex-A8, support security and non-security mode, switch by software Interrupt controller, support some registers and dedicated interrupt sources to work only in security mode DMAC0, support some dedicated channels work only in security mode eFuse, only accessed by Cortex-A8 in security mode Internal memory , part of space is addressed only in security mode, detailed size is software-programmable together with TZMA(trustzone memory adapter) and TZPC(trustzone protection controller)
1.1.6 Video CODEC Shared internal memory and bus interface for video decoder and encoder Video Decoder Real-time video decoder of MPEG-1, MPEG-2, MPEG-4,H.263, H.2 , AVS , VC-1 , RV , VP8 , Sorenson Spark
Error detection and concealment support for all video formats Output data structure after decoder is YCbCr 4:2:0 semi-planar to have more efficient bus usage, For H.2, YCbCr 4:0:0(monochrome) is also supported Minimum image size is 48x48 for all video formats
③
H.2 up to HP level 4.2 : 1080p@60fps (1920x1088) MPEG-4 up to ASP level 5 : 1080p@60fps (1920x1088) MPEG-2 up to MP : 1080p@60fps (1920x1088) MPEG-1 up to MP : 1080p@60fps (1920x1088) H.263 : 576p@60fps (720x576) Sorenson Spark : 1080p@60fps (1920x1088) VC-1 up to AP level 3 : 1080p@30fps (1920x1088) RV8/RV9/RV10 : 1080p@60fps (1920x1088) VP6/VP7/VP8 : 1080p@60fps (1920x1088) AVS : 1080p@60fps (1920x1088) For AVS, 4:4:4 sampling not supported For H.2, Image cropping not supported
②
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RK2906-6 Datasheet
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Video Encoder
Encoder only for H.2 (BP@level4.0, MP@level4.0,HP@level4.0) standard Only support I and P slices, not B slices
Entropy encoding is CAVLC in BP and CABAC in MP
Support error resilience based on constrained intra prediction and slices
Maximum MV length is +/- 14 pixels in vertical direction and +/-30 pixels in
horizontal direction
Motion vector pixel accuracy is up to 1/4 pixels in 720p resolution and 1/2 pixels
in 1080p resolution
12 intra prediction modes
Number of reference frames is 1
Maximum number of slice groups is 1 Input data format :
YCbCr 4:2:0 planar
YCbCr 4:2:0 semi-planar YCbYCr 4:2:2
CbYCrY 4:2:2 interleaved RGB444 and BGR444 RGB555 and BGR555 RGB565 and BGR565 RGB888 and BRG888
RGB101010 and BRG101010
Output data format : H.2 byte unit stream and H.2 NAL unit stream Image size is from 96x96 to 1920x1088(Full HD) ③
Maximum frame rate is up to 30fps@1920x1080 Bit rate supported is from 10Kbps to 20Mbps
1.1.7 JPEG CODEC
JPEG decoder
Input JPEG file : YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4 sampling formats
Output raw image : YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4 semi-planar Decoder size is from 48x48 to 8176x8176(66.8Mpixels) ④
Maximum data rate is up to 76million pixels per second Thumbnail decoding and error detection is supported Non-interleaved data order not supported
JPEG encoder Input raw image : YCbCr 4:2:0 planar
YCbCr 4:2:0 semi-planar YCbYCr 4:2:2
CbYCrY 4:2:2 interleaved RGB444 and BGR444 RGB555 and BGR555 RGB565 and BGR565 RGB888 and BRG888
RGB101010 and BRG101010
Output JPEG file : JFIF file format 1.02 or Non-progressive JPEG Encoder image size up to 8192x8192(million pixels) from 96x32
④
Maximum data rate up to 90million pixels per second
Support thumbnail insertion with RGB8bits, RGB24bits and JPEG compressed
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For MPEG-4,GMC(global motion compensation) not supported
For VC-1, upscaling and range mapping are supported in image post-processor For MPEG-4 SP/H.263/Sorenson spark, using a modified H.2 in-loop filter to
implement deblocking filter in post-processor unit
RK2906-6 Datasheet
1.1.8
thumbnails
Image Enhancement
Rev 1.2
Image pre-processor
Only used together with video encoder inside RK2906-6 , not support
stand-alone mode
Provides RGB to YCbCr 4:2:0 color space conversion, compatible with BT.601 ,
BT.709 or user defined coefficients
Provides YCbCr4:2:2 to YCbCr4:2:0 color space conversion
Support cropping operation from 8192x8192 to any supported encoding size Support rotation with 90 or 270 degrees
Video stabilization
Work in combined mode with video encoder inside RK2906-6 and stand-alone mode
Maximum stabilization displacement in pixels for two sequential input video pictures is +/- 16 pixels
Adaptive motion compensation filter
Offset around stabilized picture is minimum 8 pixels in standalone mode and 16 pixels in combined mode
Support scene detection from video sequence, encodes key frame when scene change noticed
Image post-processor
Combined with video/jpeg decoder, post-processor can read input data directly from decoder output to reduce bus bandwidth Also work as a stand-alone mode, its input data is from a camera interface or other image data stored in external memory Input data format :
any format generated by video decoder in combined mode YCbCr 4:2:0 semi-planar YCbCr 4:2:0 planar YCbYCr 4:2:2 YCrYCb 4:2:2 CbYCrY 4:2:2 CrYCbY 4:2:2 Ouput data format: YCbCr 4:2:0 semi-planar YCbYCr 4:2:2 YCrYCb 4:2:2 CbYCrY 4:2:2 CrYCbY 4:2:2 Fully configurable ARGB channel lengths and locations inside 32bits, such as ARGB 32bit(8-8-8-8),RGB 16bit(5-6-5),ARGB 16bit(4-4-4-4) Input image size: Combined mode : from 48x48 to 8176x8176 (66.8Mpixels)
Stand-alone mode : width from 48 to 8176,height from 48 to 8176, and
maximum size limited to 16.7Mpixels Step size is 16 pixels
Output image size: from 16x16 to 1920x1088 (horizontal step size 8,vertical
step size 2)
Support image up-scaling :
Bicubic polynomial interpolation with a four-tap horizontal kernel and a
two-tap vertical kernel
Arbitrary non-integer scaling ratio separately for both dimensions Maximum output width is 3x input width
Maximum output height is 3x input height, and 2.5x input height when
running RV/VP7/VP8 format decoder
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Rev 1.2
Support image down-scaling:
Arbitrary non-integer scaling ratio separately for both dimensions Unlimited down-scaling ratio
Not allowed to perform horizontal up-scaling and vertical down-scaling at the
same time
Support YCbCr to RGB color conversioin, compatible with BT.601-5 ,BT.709 and
user definable conversion coefficient
Support dithering (2x2 ordered spatial dithering for 4,5,6bit RGB channel
precision
Support programmable alpha channel and alpha blending operation with the
following overlay input formats:
8bit alpha value+YCbCr4:4:4,big endian channel order being AYCbCr, 8bits
each
8bit alpha value+24bit RGB,big endian channel order being ARGB,8bits each Support deinterlacing with conditional spatial deinterlace filtering, only compatible with YCbCr4:2:0 input format
Support RGB image contrast / brightness / color saturation adjustment Support image cropping & digital zoom only for JPEG or stand-alone mode Support picture in pcture
Support image rotation (horizontal flip, vertical flip, rotation 90,180 or 270 degrees)
1.1.9 Graphics Engine
Compatible with OpenGL ES2.0 , OpenGL ES1.1, OpenVG1.1, DirectFB, GDI/DirectDraw, EGL1.4 Support shader model3.0 Geometry rate : 60M tri/s
Depth-only Pixel rate : 600M pix/s Textured Pixel rate : 600M pix/s Vertex rate : 300M vert/s 2D Graphics Engine :
Bit Blit, Stretch Blit, Filter Blit Rectangle fill and clear Line drawing Copy bit Filter
High-performance stretch and shrink Monochrome expansion for text rendering ROP2,ROP3,ROP4 full alpha blending and transparency Alpha blending modes including Java 2 Porter-Duff compositing blending rules, chroma key, and pattern mask Transparency by monochrome mask 32K x 32K raster 2D coordinate system 90,180 and 270 degrees rotation on every 2D primitive Programmable high quality 9-tap,32-phase filter to support image scaling Blending, scaling and rotation are supported in one pass for stretch Blit Source format :
RGBA4444,5551,8888 RGBX4444,5551,8888 RGB565
UYVY4:2:2, YUY2(4:2:2),YV12(4:2:0) Destination formats :
RGBA4444,5551,8888 RGBX4444,5551,8888 RGB565
3D Graphics Engine :
IEEE 32-bit floating-point pipeline
Ultra-threaded, unified vertex and fragment shaders
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RK2906-6 Datasheet
Rev 1.2
Low CPU loading and low bandwidth at both high and low data rates Up to 12 programmable elements per vertex
Dependent texture operation with high-performance Alpha blending
Support video texture
Depth and stencil compare
Support for 8 fragment shader simultaneous textures Support for 12 vertex shader simultaneous textures
Point sampling,bit-linear sampling,tri-linear filtering and cubic textures Resolve and fast clear
8k x 8k texture size and 8k x 8k rendering target
1.1.10 Video IN/OUT
Camera Interface
Support CMOS type image sensor interface Support CCIR656 interface
Support CCIR656 YCbCr 4:2:2 raster video input for 8bit mode in 525/60 NTSC and 625/50 PAL video system
Data input clock is 24MHz/48MHz for sensor, and max up to 96MHz for raw data Provide YUV 4:2:2/4:2:0 output
Support up to 3856x27 resolution and maximum 10M pixels Support YUYV/UYVY format input
In sensor mode, support software-programmable vsync and href high active or low active
Embedded AXI bits master interface to improve performance, also compatible with AHB 32bits master interface
Display Interface
Image Post-Processor (IPP)
memory to memory mode input data format and size
RGB888 : 16x16 to 8191x8191 RGB565 : 16x16 to 8191x8191 YUV422/YUV420 : 16x16 to 8190x8190 YUV444 : 16x16 to 8190x8190 pre scaler
integer down-scaling(ratio: 1/2,1/3,1/4,1/5,1/6,1/7,1/8) with linear filter deinterlace(up to 1080i) to support YUV422&YUV420 input format post scaler down-scaling with 1/2 ~ 1 arbitary non-integer ratio up-scaling with 1~4 arbitary non-integer ratio 4-tap vertical, 2-tap horizontal filter The max output image width of post scaler is 4096
Support rotation with 90/180/270 degrees and x-mirror, y-mirror LCD Controller
Display Interface
Parallel RGB LCD Interface:
24bit(RGB888) 18bit(RGB666) 16bit(RGB565)
Serial RGB LCD Interface:
3x8bit (RGB delta support) 3x8bit + dummy 16bit + 8bit
MCU LCD interface:
I-8080 (up to 24-bit RGB) Hold/Auto/Bypass modes
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RK2906-6 Datasheet
Rev 1.2
1.1.11 Audio Interface TV interface : ITU-R BT.656(8-bits, 480i/576i/1080i) Display Process
One background layer: programmable 24-bit color One video layer(win0)
ARGB888, RGB565, YCbCr422, YCbCr420, YCbCr444, AYCbCr maximum resolution is 1920x1080 virtual display
1/8 to 8 scaling-down and scaling-up engine with arbitrary
non-integer ratio
256 level alpha blending(no scaling in ARGB/AYCbCr mode) transparency color key
deflicker support for interlace output sharp/smooth filter One graphic layer(win1)
RGB888, ARGB888, RGB565
maximum resolution is 1920x1080 virtual display
256 level alpha blending transparency color key One OSD layer(win2)
1/2/4/8bpp palette mode
maximum resolution is 1920x1080 8-bit alpha Alpha
transparency color key Hardware cursor(HWC)
32x32x2bpp
3-color and transparent mode 2-color + transparency + tran_invert mode 16 level alpha blending 3 x 256 x 8 bits display LUTs Graphic layer and video layer overlay exchangeable Support color space conversion : YCbCr-to-RGB(rec601-mpeg/ rec601-jpeg/rec709) and RGB-to-YCbCr
Support replication(16-bit to 24-bit) and dithering(24-bit to 16-bit/18-bit) operation
Blank and black display Standby mode Two I2S/PCM with 2ch Compatible audio resolution from 16bits to 32bits Sample rate up to 192KHz Provides master and slave work mode, software configurable Embedded 4 TX FIFO and 1 RX FIFO with 32x32bits size Support I2S normal , left-justified , right-justified three data formats in I2S mode
Support early , late1 , late2 , late3 four data formats in PCM mode
In master TX mode, Support I2S and PCM work simultaneously in condition of
same audio data and same sample rate , and only use two channels separately for I2S and PCM
Support SCLK and LRCK polarity software-configurable SCLK can be even-divided by 2 to from i2s main clock
SPDIF
Embedded one 32x32bits buffer
Provides audio data with biphase encode Support stereo voice replay with 2 channels
Support software configurable sample rates (48KHz, 44.1KHz, 32KHz)
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RK2906-6 Datasheet
Rev 1.2
1.1.12 Connectivity
Support audio data width 16bits/20bits/24bits Frame frequency is 128x audio data sample rates
SDIO interface
Compatible with SDIO ver1.00
One AHB slave interface to complete data transfer together with external DMAC1
or CPU
Support combined single FIFO(32x32bits) for both transmit and receive
operations
Support FIFO over-run and under-run prevention by stopping card clock
automatically
Support CRC generation and error detection
Embedded clock frequency division control to provide programmable baud rate Support host pull-up control, card detection and initialization, write protection Support block size from 1 to 65535Bytes
Data bus width is flexible to support 1bit/4bits Support SDIO suspend and resume operation Support SDIO read wait
SPI Controller
Two on-chip SPI controller inside RK2906-6
Support serial-master and serial-slave mode, software-configurable DMA-based or interrupt-based operation
Embedded two 32x16bits FIFO for TX and RX operation respectively Support 2 chip-selects output in serial-master mode
UART Controller
Four on-chip UART controller inside RK2906-6 DMA-based or interrupt-based operation Embedded two 32Bytes FIFO for TX and RX operation respectively Support 5bit,6bit,7bit,8bit serial data transmit or receive Standard asynchronous communication bits such as start, stop and parity Support different input clock for UART operation to get up to 4Mbps or other special baud rate
Support non-integer clock divides for baud clock generation Support IrDA1.0 SIR(115.2Kbps) mode for UART1 Auto flow control mode is only for UART0,UART2,UART3
I2C controller Four on-chip I2C controller in RK2906-6 Multi-master I2C operation Support 7bits and 10bits address mode Software programmable clock frequency and transfer rate up to 400Kbit/s in the fast mode Serial 8bits oriented and bidirectional data transfers can be made at up to
100Kbit/s in the standard mode
GPIO
7 groups of GPIO (GPIO0~GPIO6) , 32 GPIOs per group, totally have 224 GPIOs All of GPIOs can be used to generate interrupt to cortex-A8
In power-down mode, status(IO direction and output level) of GPIO0~GPIO5
can be controlled by another registers in always-on domain
Totally 96 GPIOs(GPIO0,GPIO4,GPIO6) can be used to wakeup system from stop
mode or power-down mode
All of pull-up GPIOs are software-programmable for pull-up resistor or not
All of pull-down GPIOs are software-programmable for pull-down resistor or not All of GPIOs are pull-up or pull-down in default except GPIO1[5] MUX with PWM3
Rockchips Confidential 17
RK2906-6 Datasheet
Rev 1.2
after power-on-reset
All of GPIOs are always in input direction in default after power-on-reset
USB Host1.1
Compatible with USB host1.1 specification
Only supports full-speed transfer up to 12Mbps Provides 6 host mode channels Support periodic out channel
USB Host2.0
Compatible with USB host2.0 specification
Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps)
mode
Provides 3 host mode channels
USB OTG2.0
Compatible with USB otg2.0 specification
Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps) mode
Support up to 6 device mode endpoints in addition to control endpoint 0 Support up to 4 device mode IN endpoints including control endpoint 0 Endpoints 1/3/5 can be used only as data IN endpoint Endpoints 2/4/6 can be used only as data OUT endpoint Provides 6 host mode channels
Support periodic out channel in host mode
1.1.13 Others
SAR-ADC(Successive Approximation Register) 4-channel single-ended 10-bit SAR analog-to-digital converter Conversion speed range is from 0.1 to 1 MSPS SAR-ADC clock must be less than 1MHz DNL less than ±1 LSB , INL less than ±2.0 LSB Power down current is about 1uA 2.5V Power supply for analog interface
eFuse
1024bits (128x8) high-density electrical Fuse Programming condition : VQPS must be 2.5V(±10%) Program time is about 4~6us Read condition : VQPS must be 0V or floating or 2.5V(±10%) Provide power-down and standby mode Package Type TFBGA512 (body: 16mm x 16mm ; ball size : 0.3mm ; ball pitch : 0.65mm)
Notes :
① :
DDRII and LPDDR are not used simultaneously as well as async and sync DDR NAND flash
In RK2906-6, Video decoder and encoder are not used simultaneously because of shared
internal buffer
③:
Actual maximum frame rate will depend on the clock frequency and system bus performance
④:
②:
Actual maximum data rate will depend on the clock frequency and JPEG compression rate
Rockchips Confidential 18
RK2906-6 Datasheet 1.2
Block Diagram
Rev 1.2
The following diagram shows the basic block diagram for RK2906-6.
System PeripheralClock & ResetRK2906-6Cortex-A8 32KB ICache 32KB DCacheETMNEONConnectivityUSB HOST 1.1 PMUUSB OTG 2.0PLL x 4USB HOST 2.0System registerI2S/PCM (M/S) (2ch) 512KB L2 CacheTrustZone I2S/PCM (M/S) (2ch ) Timerx4PWMx3Multi-Media Processor2D Graphics Engine3D Graphics EngineSPDIF (1ch)WatchDogUARTx4SAR-ADCJPEG DecoderInterrupt ControllerImage pre processorDMACx2 (13ch)1080p Video decoder(H263/H2/MPEG2/MPEG4/VC-1/VP8/RMVB/AVS)JPEG EncoderSPI(M/S) x2Image post processorModem I/F1080p Video encoder(H.2)I2C x4Image InterfaceCamera I/F(8bits CCIR / 8bits Sensor)GPIOExternal Memory InterfaceMemorySDR/DDR/LBA Nand Flash (24bit ECC)LCD Controller(1920x1080 output24 bits panel4-layer windowScale up/Down)SD2.0 / HS-MMC4.2 (8bits)SRAM (16KB)(security/non-security)ROM (10KB)DDRIII, DDRII (400MHz, 32bits/16bits)LPDDR (200MHz, 32bits)eFuse (128 x 8bits )Fig. 1-1 RK2906-6 Block Diagram
Rockchips Confidential 19
RK2906-6 Datasheet
Rev 1.0
Chapter 2 Package Description 2.1 GPIO1_C[0]/UARTA GPIO6_A[0] GPIO6_B[7] 0_CTS_N LRCK_TX SDO MC1_PWR_EN 0_PWR_EN 3_SIN _EN/PWM3 GPIO2_A[3]/SDMMC0_GPIO2_A[7]/UARTB GPIO6_B[6] GPIO6_B[5] GPIO6_A[1] 2_RTS_N SDI SCLK UART1_SIR_IN SDA T1_SIR_OUT GPIO1_C[1]/UARTC GPIO6_A[5] GPIO6_B[4] GPIO6_A[2] 0_RTS_N 2_CTS_N LRCK_RX GPIO2_B[4]/UARTGPIO1_B[7]/UARTD GPIO6_A[6] GPIO6_A[7] GPIO6_B[3] GPIO6_A[3] 0_SOUT A 3_CTS_N/I2C3_SDK 0_SIN GPIO3_A[0]/I2S1_CLGPIO1_B[6]/UARTGPIO5_D[4]/I2C2_SCL SCL DCLK GPIO2_B[7]/I2C0_GPIO0_A[7]/MII_MGPIO4_D[0] SIN GPIO2_A[6]/UARTGPIO3_A[2]/I2S1_GPIO2_A[4]/UART1_GPIO1_B[5]/PWM0 GPIO2_B[6]/I2C0_SDA GPIO4_D[4] GPIO6_C[6] GPIO6_C[0] GPIO3_A[3]/I2S1_GPIO3_A[1]/I2S1_GPIO5_D[2]/PWM1/GPIO5_D[3]/I2C2_WRITE_PRT/PWM2/UARC0_DETECT_N _DRV_VBUS SCL GPIO2_A[2]/SDMMGPIO4_A[6]/OTG1GPIO1_A[7]/I2C1_GPIO3_A[5]/I2S1_GPIO3_A[4]/I2S1_GPIO5_D[6]/SDMGPIO5_D[5]/SDMMCGPIO2_B[2]/UARTGPIO1_A[5]/EMMC_PWRNC GPIO6_C[2] SDA GPIO1_A[6]/I2C1_Ball Map 1 2 3 4 5 6 7 8 9 10 11 12 GPIO2_B[0]/UARTE GPIO6_B[0] GPIO5_A[0] GPIO6_B[2] GPIO5_A[2] GPIO6_A[4] 2_SIN GPIO2_B[5]/UART3_RTS_N/I2C3_SCL GPIO2_B[1]/UART2_SOUT GPIO2_A[5]/UART1_SOGPIO6_C[5] UT GPIO4_D[1] GPIO6_C[1] GPIO2_B[3]/UARTF GPIO6_B[1] GPIO0_A[1] GPIO5_A[1] GPIO0_A[0] AVDD_DPLL AHVDD_APLL AHVSS_APLL 3_SOUT GPIO4_D[3] GPIO4_D[2] GPIO4_D[5] GPIO5_D[7] G XOUT24M XIN24M GPIO0_A[2] GPIO0_A[4] DVDD_APLL AVSS_DPLL DVSS_APLL VDDIO_AP1 VDDIO_AP0 VDDCORE VDDIO6 VDDCORE H NC NC GPIO0_A[3] GPIO4_A[3] DVDD_DPLL DVSS_DPLL DVSS_CGPLL NP NP NP NP NP J GPIO4_A[0] GPIO4_A[1] GPIO4_A[2] GPIO4_A[4] AVDD_CGPLL DVDD_CGPLL AVSS_CGPLL NP NP NP NP NP K DQ[3] DQ[2] DQ[1] DQ[0] NC NPOR VDDIO0 NP NP GND GND GND L DQS[0] DQS_b[0] DQ[5] DQ[4] NC NC VDDCORE NP NP GND GND GND M DQ[7] DQ[6] NC DM[0] VSSIO_DDR0 NC MC NP NP GND GND GND Rockchips Confidential 20
RK2906-6 Datasheet
13 14 15
Rev 1.0
16 17 18 19 20 21 22 23 24 GPIO2_C[5]/SPNC I1_CSN0 NC NC NC NC NC NC GPIO2_D[2]/I2S0_LRCK_NC RX/MII_TX_ERR NC NC A GPIO2_C[6]/SNC NC NC PI1_TXD NC GPIO5_A[3]/MII_NC TX_CLKIN NC NC GPIO2_D[3]/I2S0_SNC DI/MII_COL GPIO1_D[4]/SDMMC0_B DATA2 GPIO2_C[7]/SPNC I1_RXD GPIO4_A[7]/SPDIF_TX NC NC NC NC NC GPIO2_D[4]/I2S0_SDO0/NC MII_RXD2 NC NC C GPIO2_C[0]/SPGPIO6_C[3] I0_CLK GPIO2_C[3]/SPI0_RXD NC NC GPIO0_A[6]/MII_NC MD GPIO1_D[2]/SDMMC0_NC DATA0 GPIO1_D[0]/SDMMNC C0_CLKOUT NC D GPIO2_C[1]/SPGPIO6_C[7] I0_CSN0 GPIO2_C[2]/SPI0_TXD NC NC NC NC GPIO1_D[7]/SDMMC0_NC DATA5 NC NC GPIO2_D[0]/I2S0_CLK/E MII_RX_CLKIN GPIO1_A[3]/EMMC_DETECGPIO6_C[4] NC T_N/SPI1_CSN1 GPIO2_C[4]/SNC PI1_CLK NC NC GPIO4_D[6]/I2S0_LRCNC K_TX0 NC NC NC F GPIO4_A[5]/OTG0VDDIO5 VDDCORE VDDIO4 VDDCORE _DRV_VBUS VDDIO3 GPIO1_D[5]/SDMMC0_DATA3 GPIO1_D[1]/SDMMC0_NC CMD GPIO1_D[3]/SDMMNC C0_DATA1 NC G GPIO2_D[1]/I2S0_SCLNP NP NP NP NP NC NC K/MII_CRS NC NC NC NC H GPIO0_D[6]/FLASNP NP NP NP NP VDDCORE H_CSN5 GPIO1_A[0]/FLASH_CSGPIO0_A[5]/FLASH_DQS N7/MDDR_TQ GPIO0_D[5]/FLASHNC _CSN4 NC J GPIO0_D[3]/FLASHGND GND GND NP NP VDDIO2 FLASH_WP FLASH_WRN NC _CSN2 GPIO0_D[4]/FLASH_CSN3 GPIO0_D[2]/FLASH_CSK N1 GPIO0_D[7]/FLASH_CSGND GND GND NP NP VDDCORE FLASH_DATA[6] NC FLASH_DATA[7] FLASH_DATA[2] FLASH_DATA[3] N6 L GND GND GND NP NP VDDIO_FLASH1 NC NC FLASH_CLE NC FLASH_DATA[5] FLASH_CSN0 M Rockchips Confidential 21
RK2906-6 Datasheet
N NC NC NC
Rev 1.0
NC VDDIO_DDR0 NC VDDCORE NP NP GND GND GND P NC NC NC NC VSSIO_DDR1 VREF0 NC NP NP GND GND GND R NC NC BA[0] ZQ_PIN VDDIO_DDR1 NC VDDCORE NP NP GND GND GND T A[1] A[0] BA[1] BA[2] VSSIO_DDR2 NC NC NP NP NP NP NP U A[2] A[3] NC0 NC1 VDDIO_DDR2 VREF1 VDDCORE NP NP NP NP NP V A[6] CS_B0 A[4] A[5] VSSIO_DDR3 RESET NC GPIO6_D[2] GPIO6_D[0] VDDCORE VDDIO_LCD0 VDDCORE LCDC_DATA[0]/EW NC ODT0 NC RET_EN VDDIO_DDR3 VREF2 GPIO6_D[3] GPIO6_D[1] NC6 BC_SDDO[0] LCDC_HSYNC/EBC_SDLE LCDC_DATA[18]/LCDC_DATA[23]/EBC_GDRL LCDC_DATA[9]/EBC_SDCE1 LCDC_DCLK/EBC_SDCLK LCDC_DATA[3]/EBC_SDDO[3] LCDC_DATA[2]/EBC_SDDO[2] LCDC_DATA[6]/EBC_SDDO[6] Y CK CK_B CKE0 NC VSSIO_DDR4 VDDIO_DDR4 VSSIO_DDR5 VDDIO_DDR5 VSSIO_DDR6 VDDIO_DDR6 EBC_GDPWR2 LCDC_DATA[20]/AA WE_B CAS_B NC NC3 NC DQ[12] DQ[13] NC4 NC NC EBC_SDSHR LCDC_DATA[5]/EAB A[10] RAS_B NC2 A[14] DQ[9] DQ[10] NC NC5 NC NC BC_SDDO[5] LCDC_DATA[1]/EAC A[8] A[13] A[7] DQ[8] DM[1] DQS_b[1] DQ[14] NC NC NC BC_SDDO[1] LCDC_DATA[4]/EAD A[11] NC A[9] A[12] DQ[11] DQS[1] DQ[15] NC NC NC BC_SDDO[4] 1 2 3 4 5 6 7 8 9 10 11 12 Rockchips Confidential 22
RK2906-6 Datasheet
GND GND GND
Rev 1.0
NP NP VDDCORE FLASH_DATA[1] FLASH_RDY FLASH_RDN NC FLASH_DATA[0] FLASH_DATA[4] N GND GND GND NP NP VDDIO_FLASH0 FLASH_ALE VDDCORE_EFUSE VDDIO_RTC NC NC NC P GND GND GND NP NP VDDCORE NC EFUSE_VQPS VSSIO_UHOST VDDIO_UHOST USBHOST_DN USBHOST_DP R NP NP NP NP NP VDDIO1 VDDIO_EFUSE OTG1_ID OTG1_VSSA OTG1_VDD25 OTG1_DM OTG1_DP T NP NP NP NP NP VDDCORE_RTC OTG1_DVDD OTG1_VSSAC OTG1_DVSS OTG1_VBUS OTG1_VDD33 OTG1_RKELVIN U VDDIO_LCD1 VDDCORE VDDIO_VIP VDDCORE VDDIO_SMC0 VDDIO_SMC1 OTG0_DVDD OTG0_ID OTG0_VSSA OTG0_VDD25 OTG0_DM OTG0_DP V LCDC_DATA[22]/EBC_GDSP LCDC_DATA[19]/EBC_VCOM LCDC_DATA[10]/EBC_SDCE2 LCDC_VSYNC/EBC_SDOE LCDC_DATA[7]/EBC_SDDO[7] LCDC_DATA[8]/EBC_SDCE0 LCDC_DATA[21]/EVIP_DATAIN[4] BC_GDOE LCDC_DEN/EBC_GVIP_DATAIN[11] DCLK LCDC_DATA[14]/EVIP_DATAIN[10] BC_BORDER0 LCDC_DATA[11]/EBC_SDCE3 LCDC_DATA[12]/EBC_SDCE4 LCDC_DATA[13]/EBC_SDCE5 LCDC_DATA[15]/EGPIO1_B[4]/VIP_CNC LKOUT NC NC OTG0_VSSAC OTG0_DVSS OTG0_VBUS OTG0_VDD33 OTG0_RKELVIN W VIP_DATAIN[7] NC NC NC NC NC NC SARADC_AIN[1] SARADC_AIN[2] Y NC NC NC NC NC NC NC SARADC_AIN[0] SARADC_AIN[3] AA VIP_DATAIN[5] BC_BORDER1 LCDC_DATA[16]/EVIP_DATAIN[6] BC_GDPWR0 LCDC_DATA[17]/EVIP_DATAIN[9] BC_GDPWR1 VIP_DATAIN[8] VIP_VSYNC NC NC NC NC NC VDDA_SARADC AB VIP_HREF NC NC NC NC NC NC NC AC VIP_CLKIN NC NC NC NC NC NC NC AD 13 14 15 16 17 18 19 20 21 22 23 24 Fig. 2-1 RK2906-6 Ball Mapping Diagram
Rockchips Confidential 23
RK2906-6 Datasheet 2.2
Ball # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18
Rev 1.0
Pin Number Order
Table 2-1 RK2906-6 Pin Number Order Information Pin Name GPIO6_A[0] GPIO6_B[7] GPIO1_C[0]/UART0_CTS_N/SDIO_DETECT_N GPIO3_A[5]/I2S1_LRCK_TX GPIO3_A[4]/I2S1_SDO GPIO5_D[6]/SDIO_PWR_EN GPIO5_D[5]/SDMMC_PWR_EN GPIO2_B[2]/UART3_SIN GPIO1_A[5]/EMMC_PWR_EN/PWM3 NC GPIO6_C[2] GPIO1_A[6]/I2C1_SDA GPIO2_C[5]/SPI1_CSN0 NC NC NC NC NC NC NC NC NC NC NC GPIO6_A[5] GPIO6_B[4] GPIO6_A[2] GPIO1_C[1]/UART0_RTS_N/SDIO_WRITE_PRT GPIO2_A[6]/UART2_CTS_N GPIO3_A[2]/I2S1_LRCK_RX GPIO2_A[4]/UART1_SIN GPIO1_B[5]/PWM0 GPIO2_B[6]/I2C0_SDA GPIO4_D[4] GPIO6_C[6] GPIO6_C[0] NC GPIO2_C[7]/SPI1_RXD GPIO4_A[7]/SPDIF_TX GPIO5_A[4]/TS_SYNC NC NC Ball # B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 Pin Name GPIO6_B[6] GPIO6_B[5] GPIO6_A[1] GPIO2_A[7]/UART2_RTS_N GPIO3_A[3]/I2S1_SDI GPIO3_A[1]/I2S1_SCLK GPIO5_D[2]/PWM1/UART1_SIR_IN GPIO5_D[3]/I2C2_SDA GPIO2_A[3]/SDMMC_WRITE_PRT/PWM2/UART1_SIR_OUT GPIO2_A[2]/SDMMC_DETECT_N GPIO4_A[6]/OTG1_DRV_VBUS GPIO1_A[7]/I2C1_SCL NC NC NC GPIO2_C[6]/SPI1_TXD NC GPIO5_A[3]/MII_TX_CLKIN NC NC NC GPIO2_D[3]/I2S0_SDI/MII_COL NC GPIO1_D[4]/SDMMC_DATA2 GPIO6_A[6] GPIO6_A[7] GPIO6_B[3] GPIO6_A[3] GPIO1_B[7]/UART0_SOUT GPIO2_B[4]/UART3_CTS_N/I2C3_SDA GPIO3_A[0]/I2S1_CLK GPIO1_B[6]/UART0_SIN GPIO5_D[4]/I2C2_SCL GPIO2_B[7]/I2C0_SCL GPIO0_A[7]/MII_MDCLK GPIO4_D[0] GPIO6_C[3] GPIO2_C[0]/SPI0_CLK GPIO2_C[3]/SPI0_RXD NC NC GPIO0_A[6]/MII_MD Rockchips Confidential 24
RK2906-6 Datasheet
C19 C20 C21 C22 C23 C24 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 NC NC GPIO2_D[4]/I2S0_SDO0/MII_RXD2 NC NC NC GPIO6_B[0] GPIO5_A[0] GPIO6_B[2] GPIO5_A[2] GPIO6_A[4] GPIO2_B[0]/UART2_SIN
D19 D20 D21 D22 D23 D24 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 H1 H2 H3 H4 H5 H6 H7 H18 H19 H20 H21 H22 H23 H24 K1 K2
Rev 1.0
NC GPIO1_D[2]/SDMMC_DATA0 NC GPIO1_D[0]/SDMMC_CLKOUT NC NC GPIO6_B[1] GPIO0_A[1] GPIO5_A[1] GPIO0_A[0] AVDD_DPLL AHVDD_APLL AHVSS_APLL GPIO2_B[3]/UART3_SOUT GPIO4_D[3] GPIO4_D[2] GPIO4_D[5] GPIO5_D[7] GPIO6_C[4] NC GPIO1_A[3]/EMMC_DETECT_N/SPI1_CSN1 GPIO2_C[4]/SPI1_CLK NC NC NC GPIO4_D[6]/I2S0_LRCK_TX0 NC NC NC NC NC NC GPIO0_A[3] GPIO4_A[3] DVDD_DPLL DVSS_DPLL DVSS_CGPLL NC NC GPIO2_D[1]/I2S0_SCLK/MII_CRS NC NC NC NC DQ[3] DQ[2] GPIO2_B[5]/UART3_RTS_N/I2C3_SCL GPIO2_B[1]/UART2_SOUT GPIO2_A[5]/UART1_SOUT GPIO6_C[5] GPIO4_D[1] GPIO6_C[1] GPIO6_C[7] GPIO2_C[1]/SPI0_CSN0 GPIO2_C[2]/SPI0_TXD NC NC NC NC GPIO1_D[7]/SDMMC_DATA5 NC NC NC GPIO2_D[0]/I2S0_CLK/MII_RX_CLKIN XOUT24M XIN24M GPIO0_A[2] GPIO0_A[4] DVDD_APLL AVSS_DPLL DVSS_APLL VDDIO_AP1 VDDIO_AP0 VDDCORE VDDIO6 VDDCORE VDDIO5 VDDCORE VDDIO4 VDDCORE Rockchips Confidential 25
RK2906-6 Datasheet
G17 G18 G19 G20 G21 G22 G23 G24 J1 J2 J3 J4 J5 J6 J7 J18 J19 J20 J21 J22 J23 J24 L1 L2 L3 L4 L5 L6 L7 L10 L11 L12 L13 L14 L15 L18 L19 L20 L21 L22 L23 L24 N1 N2 N3 N4 GPIO4_A[5]/OTG0_DRV_VBUS VDDIO3 GPIO1_D[5]/SDMMC_DATA3 GPIO1_D[1]/SDMMC_CMD NC GPIO1_D[3]/SDMMC_DATA1 NC NC GPIO4_A[0] GPIO4_A[1] GPIO4_A[2] GPIO4_A[4] AVDD_CGPLL DVDD_CGPLL AVSS_CGPLL VDDCORE GPIO0_D[6]/FLASH_CSN5
K3 K4 K5 K6 K7 K10 K11 K12 K13 K14 K15 K18 K19 K20 K21 K22 K23 K24 M1 M2 M3 M4 M5 M6 M7 M10 M11 M12 M13 M14 M15 M18 M19 M20 M21 M22 M23 M24 P1 P2 P3 P4 P5 P6 P7 P10
Rev 1.0
DQ[1] DQ[0] NC NPOR VDDIO0 GND GND GND GND GND GND VDDIO2 FLASH_WP FLASH_WRN GPIO4_B[6]/FLASH_DATA[14] GPIO0_D[3]/FLASH_CSN2 GPIO0_D[4]/FLASH_CSN3 GPIO0_D[2]/FLASH_CSN1 DQ[7] DQ[6] NC DM[0] VSSIO_DDR0 NC NC GND GND GND GND GND GND VDDIO_FLASH1 NC NC FLASH_CLE NC FLASH_DATA[5] FLASH_CSN0 NC NC NC NC VSSIO_DDR1 VREF0 NC GND GPIO1_A[0]/FLASH_CSN7/MDDR_TQ GPIO0_A[5]/FLASH_DQS GPIO0_D[5]/FLASH_CSN4 NC NC DQS[0] DQS_B[0] DQ[5] DQ[4] NC NC VDDCORE GND GND GND GND GND GND VDDCORE FLASH_DATA[6] NC FLASH_DATA[7] FLASH_DATA[2] FLASH_DATA[3] GPIO0_D[7]/FLASH_CSN6 NC NC NC NC Rockchips Confidential 26
RK2906-6 Datasheet
N5 N6 N7 N10 N11 N12 N13 N14 N15 N18 N19 N20 N21 N22 N23 N24 R1 R2 R3 R4 R5 R6 R7 R10 R11 R12 R13 R14 R15 R18 R19 R20 R21 R22 R23 R24 U1 U2 U3 U4 U5 U6 U7 U18 U19 U20 VDDIO_DDR0 NC VDDCORE GND GND GND GND GND GND VDDCORE FLASH_DATA[1] FLASH_RDY FLASH_RDN NC FLASH_DATA[0] FLASH_DATA[4] NC NC BA[0] ZQ_PIN VDDIO_DDR1 NC VDDCORE GND GND GND GND GND GND VDDCORE
P11 P12 P13 P14 P15 P18 P19 P20 P21 P22 P23 P24 T1 T2 T3 T4 T5 T6 T7 T18 T19 T20 T21 T22 T23 T24 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20
Rev 1.0
GND GND GND GND GND VDDIO_FLASH0 FLASH_ALE VDDCORE_EFUSE VDDIO_RTC NC NC NC A[1] A[0] BA[1] BA[2] VSSIO_DDR2 NC NC VDDIO1 VDDIO_EFUSE OTG1_ID OTG1_VSSA OTG1_VDD25 OTG1_DM OTG1_DP A[6] CS_B0 A[4] A[5] VSSIO_DDR3 RESET NC GPIO6_D[2] GPIO6_D[0] VDDCORE VDDIO_LCD0 VDDCORE VDDIO_LCD1 VDDCORE VDDIO_VIP VDDCORE VDDIO_SMC0 VDDIO_SMC1 OTG0_DVDD OTG0_ID GPIO3_D[6]/SMC_ADDR[8]/HOST_DATA[8] EFUSE_VQPS VSSIO_UHOST VDDIO_UHOST USBHOST_DN USBHOST_DP A[2] A[3] NC0 NC1 VDDIO_DDR2 VREF1 VDDCORE VDDCORE_RTC OTG1_DVDD OTG1_VSSAC Rockchips Confidential 27
RK2906-6 Datasheet
U21 U22 U23 U24 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 OTG1_DVSS NC OTG1_VDD33 OTG1_RKELVIN NC ODT0 NC RET_EN VDDIO_DDR3 VREF2 GPIO6_D[3] GPIO6_D[1] NC6 LCDC_DATA[0]/EBC_SDDO[0] LCDC_HSYNC/EBC_SDLE LCDC_DATA[23]/EBC_GDRL LCDC_DATA[22]/EBC_GDSP LCDC_DATA[21]/EBC_GDOE VIP_DATAIN[4] GPIO1_B[4]/VIP_CLKOUT NC NC NC OTG0_VSSAC OTG0_DVSS OTG0_VBUS OTG0_VDD33 OTG0_RKELVIN WE_B CAS_B NC NC3 NC DQ[12] DQ[13] NC4 NC NC LCDC_DATA[20]/EBC_SDSHR LCDC_DCLK/EBC_SDCLK LCDC_DATA[10]/EBC_SDCE2 LCDC_DATA[14]/EBC_BORDER0 VIP_DATAIN[10] NC NC NC
V21 V22 V23 V24 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18
Rev 1.0
OTG0_VSSA OTG0_VDD25 OTG0_DM OTG0_DP CK CK_B CKE0 NC VSSIO_DDR4 VDDIO_DDR4 VSSIO_DDR5 VDDIO_DDR5 VSSIO_DDR6 VDDIO_DDR6 LCDC_DATA[18]/EBC_GDPWR2 LCDC_DATA[9]/EBC_SDCE1 LCDC_DATA[19]/EBC_VCOM LCDC_DEN/EBC_GDCLK VIP_DATAIN[11] VIP_DATAIN[7] NC NC NC NC NC NC SARADC_AIN[1] SARADC_AIN[2] A[10] RAS_B NC2 A[14] DQ[9] DQ[10] NC NC5 NC NC LCDC_DATA[5]/EBC_SDDO[5] LCDC_DATA[3]/EBC_SDDO[3] LCDC_VSYNC/EBC_SDOE LCDC_DATA[11]/EBC_SDCE3 LCDC_DATA[15]/EBC_BORDER1 VIP_DATAIN[5] VIP_DATAIN[8] VIP_VSYNC Rockchips Confidential 28
RK2906-6 Datasheet
AA19 AA20 AA21 AA22 AA23 AA24 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 NC NC GNC NC SARADC_AIN[0] SARADC_AIN[3] A[8] A[13] A[7] DQ[8] DM[1] DQS_B[1] DQ[14] NC NC NC LCDC_DATA[1]/EBC_SDDO[1] LCDC_DATA[2]/EBC_SDDO[2] LCDC_DATA[7]/EBC_SDDO[7] LCDC_DATA[12]/EBC_SDCE4 LCDC_DATA[16]/EBC_GDPWR0 VIP_DATAIN[6] VIP_HREF NC NC NC NC NC NC NC
AB19 AB20 AB21 AB22 AB23 AB24 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24
Rev 1.0
NC GNC] NC NC NC VDDA_SARADC A[11] NC A[9] A[12] DQ[11] DQS[1] DQ[15] NC NC NC LCDC_DATA[4]/EBC_SDDO[4] LCDC_DATA[6]/EBC_SDDO[6] LCDC_DATA[8]/EBC_SDCE0 LCDC_DATA[13]/EBC_SDCE5 LCDC_DATA[17]/EBC_GDPWR1 VIP_DATAIN[9] VIP_CLKIN NC NC NC NC NC NC NC 2.3 RK2906-6 power/ground IO descriptions Table 2-2 RK2906-6 Power/Ground IO informations Ball # Min(V) Typ(V) Max(V) K10,K11,K12,K13,K14,K15, L10,L11,L12,L13,L14,L15, Group Descriptions GND M10,M11,M12,M13,M14,M15, N10,N11,N12,N13,N14,N15, P10,P11,P12,P13,P14,P15, R10,R11,R12,R13,R14,R15 0 Internal Core Ground and digital IO Ground G10,G12,G14,G16, VDDCORE L7,J18,N7,L18, R7,N18,U7,R18, V10,V12,V14,V16 1.08 1.2 1.32 Internal Core Power (@ CPU frequency <= 1GHz) Rockchips Confidential 29
RK2906-6 Datasheet
VDDIO0 K7
3
3.3 Rev 1.0
3.6 Digital GPIO Power VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 T18 K18 G18 G15 G13 G11 3 3 3 3 3 3 VDDIO_LCD0 V11 3 1.62 3 1.62 VDDIO_VIP V15 3 1.62 VDDIO_SMC0 VDDIO_SMC1 V17 V18 3 3 VDDIO_FLASH0 P18 3 1.62 3 1.62 VDDIO_AP0 G9 3 1.62 3 1.62 VDDIO_DDR0 N5 1.7 1.65 1.7 1.65 1.7 1.65 1.7 1.65 1.8 1.8 1.9 1.95 DDRII (cke/cs/ret) LPDDR(cke/cs/ret) Digital IO Power DDRII/LPDDR(cke/cs/ret) Digital IO Ground 1.8 1.8 1.8 1.8 1.8 1.8 0 0 0 1.9 1.95 1.9 1.95 1.9 1.95 DDRII/LPDDR(data lane0/2/cmd lane) Digital IO Ground DDRII (data lane0/2/cmd lane) LPDDR (data lane0/2 cmd lane) Digital IO Power 3.3 1.8 3.3 1.8 3.6 1.98 3.6 1.98 I2S/UART/I2C for Mobile phone Digital IO Power 3.3 1.8 3.3 1.8 3.6 1.98 3.6 1.98 Nand Flash Digital IO Power 3.3 3.3 3.6 3.6 SMC/EBC Digital IO Power 3.3 1.8 3.6 1.98 Camera Digital IO Power 3.3 1.8 3.3 1.8 3.6 1.98 3.6 1.98 LCDC/EBC Digital IO Power 3.3 3.3 3.3 3.3 3.3 3.3 3.6 3.6 3.6 3.6 3.6 3.6 Digital GPIO Power VDDIO_LCD1 V13 VDDIO_FLASH1 M18 VDDIO_AP1 G8 VDDIO_DDR1 R5 VDDIO_DDR2 VSSIO_DDR0 VSSIO_DDR1 VSSIO_DDR2 U5 M5 P5 T5 VDDIO_DDR3 W5 VSSIO_DDR3 V5 0 Rockchips Confidential 30
RK2906-6 Datasheet
1.7 1.65 1.7 1.65 1.7 1.65
1.8 1.8 1.8 1.8 1.8 1.8 0 0 0 Rev 1.0
VDDIO_DDR4 Y6 1.9 1.95 1.9 1.95 1.9 1.95 DDRII/LPDDR(data lane1/3/cmd lane) Digital IO Ground DDRII (data lane1/3/cmd lane) LPDDR (data lane1/3 cmd lane) Digital IO Power VDDIO_DDR5 Y8 VDDIO_DDR6 VSSIO_DDR4 VSSIO_DDR5 VSSIO_DDR6 Y10 Y5 Y7 Y9 AHVSS_APLL AHVDD_APLL DVDD_APLL DVSS_APLL F7 F6 G5 G7 2.25 1.08 AVSS_DPLL AVDD_DPLL DVDD_DPLL DVSS_DPLL G6 F5 H5 H6 1.08 1.08 AVSS_CGPLL J7 0 CODEC/GENERAL PLL(1.0GHz) Analog Ground CODEC/GENERAL PLL(1.0GHz) Analog Power CODEC/GENERAL PLL(1.0GHz) Digital Power CODEC/GENERAL PLL(1.0GHz) Digital Ground 0 1.2 1.2 0 1.32 1.32 DDR PLL(1.0GHz) Analog Ground DDR PLL(1.0GHz) Analog Power DDR PLL(1.0GHz) Digital Power DDR PLL(1.0GHz) Digital Ground 0 2.5 1.2 0 2.75 1.32 ARM PLL(1.6GHz) Analog Ground ARM PLL(1.6GHz) Analog Power ARM PLL(1.6GHz) Digital Power ARM PLL(1.6GHz) Digital Ground AVDD_CGPLL J5 1.08 1.2 1.32 DVDD_CGPLL J6 1.08 1.2 1.32 DVSS_CGPLL H7 N/A N/A N/A VDDA_SARADC AB24 2.25 2.5 2.75 SAR-ADC Analog Power OTG0_VSSAC OTG0_DVSS OTG0_DVDD OTG0_VDD25 OTG0_VSSA OTG0_VDD33 W20 W21 V19 V22 V21 W23 1.116 2.325 3.069 0 0 1.2 2.5 0 3.3 1.32 2.75 3.63 USB OTG Analog Ground USB OTG Digital Ground USB OTG Digital Power USB OTG Analog Power USB OTG Analog Ground USB OTG Analog Power OTG1_VDD33 OTG1_VSSA OTG1_VDD25 OTG1_DVDD OTG1_DVSS OTG1_VSSAC U23 T21 T22 U19 U21 U20 3.069 2.325 1.116 3.3 0 2.5 1.2 0 0 3.63 2.75 1.32 USB Host2.0 Analog Power USB Host2.0 Analog Ground USB Host2.0 Analog Power USB Host2.0 Digital Power USB Host2.0 Digital Ground USB Host2.0 Analog Ground Rockchips Confidential 31
RK2906-6 Datasheet
VDDIO_UHOST VSSIO_UHOST R22 R21
3
0
3.3 Rev 1.0
3.6 USB Host1.0 Digital Power USB Host1.0 Digital Ground VDDCORE_RTC VDDIO_RTC U18 P21 1.08 3 1.62 1.2 3.3 1.8 1.32 3.6 1.98 RTC logic Digital Power RTC IO Digital Power VDDIO_EFUSE VDDCORE_EFUSE T19 P20 3 1.08 3.3 1.2 3.6 1.32 eFuse IO Digital Power eFuse logic Digital Power
Rockchips Confidential 32
RK2906-6 Datasheet
2.3.1
Rev 1.0
RK2906-6 function IO descriptions
Table 2-3 RK2906-6 IO descriptions Ball # func0 func1 func2 ④Pin Name func3 Left Side Pad types ①Drive ②pull up/down Reset state ③Power supply ⑤AHVSS_APLL AHVDD_APLL DVDD_APLL DVSS_APLL AVSS_DPLL AVDD_DPLL DVDD_DPLL DVSS_DPLL AVSS_CGPLL AVDD_CGPLL DVDD_CGPLL DVSS_CGPLL XIN24M XOUT24M NPOR TEST DQ[0] DQ[1] DQ[2] DQ[3] DM[0] DQS_B[0] DQS[0] DQ[4] DQ[5] DQ[6] F7 F6 G5 G7 G6 F5 H5 H6 J7 J5 J6 H7 G2 G1 K6 V7 K4 K3 K2 K1 M4 L2 L1 L4 L3 M2 Analog Ground 2.5V 1.2V Digital Ground Analog Ground 1.2V 1.2V Digital Ground Analog Ground 1.2V 1.2V Digital Ground XIN24M XOUT24M NPOR TEST DQ[0] DQ[1] DQ[2] DQ[3] DM[0] DQS_b[0] DQS[0] DQ[4] DQ[5] DQ[6] AG AP DP DG AG AP DP DG AG AP DP DG I O I I I/O I/O I/O I/O O I/O I/O I/O I/O I/O N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 8 8 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Down Down N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A I O I Down I Down I I I I O I I I I I VDDIO_DDR0 VDDIO_DDR1 VDDIO_DDR2 VDDIO0 PLL Domain Rockchips Confidential 33
RK2906-6 Datasheet
DQ[7] VREF0 ZQ_PIN BA[0] BA[1] BA[2] A[0] A[1] A[2] A[3] A[4] A[5] A[6] RET_EN CKE0 RESET CS_B0 VREF1 CK CK_B ODT0 WE_B RAS_B CAS_B A[7] A[8] A[9] A[10] A[11] A[12] M1 P6 R4 R3 T3 T4 T2 T1 U1 U2 V3 V4 V1 W4 Y3 V6 V2 U6 Y1 Y2 W2 AA1 AB2 AA2 AC3 AC1 AD3 AB1 AD1 AD4 DQ[7] VREF4 ZQ_PIN BA[0] BA[1] BA[2] A[0] A[1] A[2] A[3] A[4] A[5] A[6] RET_EN CKE0 RESET CS_B0 VREF4 CK CK_B ODT0 WE_B RAS_B CAS_B A[7] A[8] A[9] A[10] A[11] A[12]
Rev 1.0
I/O DP A O O O O O O O O O O I O O O DP O O O O O O O O O O O O N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A I N/A N/A O O O O O O O O O O I O O O N/A O O O O O O O O O O O O VDDIO_DDR4 VDDIO_DDR5 VDDIO_DDR6 VDDIO_DDR3 Rockchips Confidential 34
RK2906-6 Datasheet
A[13] A[14] DQ[8] DQ[9] DQ[10] DQ[11] DM[1] DQS_B[1] DQS[1] DQ[12] DQ[13] DQ[14] DQ[15] VREF2 LCDC_DATA[0] LCDC_DATA[1] LCDC_DATA[2] LCDC_DATA[3] LCDC_DATA[4] LCDC_DATA[5] LCDC_DATA[6] LCDC_DATA[7] LCDC_HSYNC LCDC_DCLK LCDC_VSYNC LCDC_DEN LCDC_DATA[8] LCDC_DATA[9] LCDC_DATA[10] LCDC_DATA[11] AC2 AB4 AC4 AB5 AB6 AD5 AC5 AC6 AD6 AA6 AA7 AC7 AD7 W6 W10 AC11 AC12 AB12 AD11 AB11 AD12 AC13 W11 AA12 AB13 Y14 AD13 Y12 AA13 AB14 A[13] A[14] DQ[8] DQ[9] DQ[10] DQ[11] DM[1] DQS_b[1] DQS[1] DQ[12] DQ[13] DQ[14] DQ[15] VREF LCDC_DATA[0] LCDC_DATA[1] LCDC_DATA[2] LCDC_DATA[3] LCDC_DATA[4] LCDC_DATA[5] LCDC_DATA[6] LCDC_DATA[7] LCDC_HSYNC LCDC_DCLK LCDC_VSYNC LCDC_DEN LCDC_DATA[8] LCDC_DATA[9] LCDC_DATA[10] LCDC_DATA[11]
Rev 1.0
O O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O DP I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I/O I/O I/O N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down O O I I I I O I I I I I I N/A I Down I Down I Down I Down I Down I Down I Down I Down O Down O Down I Down I Down I Down I Down I Down I Down VDDIO_LCD0 VDDIO_LCD1 VDDIO_DDR4 VDDIO_DDR5 VDDIO_DDR6 ebc_sddo0 ebc_sddo1 ebc_sddo2 ebc_sddo3 ebc_sddo4 ebc_sddo5 ebc_sddo6 ebc_sddo7 ebc_sdle ebc_sdclk ebc_sdoe ebc_gdclk ebc_sdce0 ebc_sdce1 ebc_sdce2 ebc_sdce3 Rockchips Confidential 35
RK2906-6 Datasheet
LCDC_DATA[12] LCDC_DATA[13] LCDC_DATA[14] LCDC_DATA[15] LCDC_DATA[16] LCDC_DATA[17] LCDC_DATA[18] LCDC_DATA[19] LCDC_DATA[20] LCDC_DATA[21] LCDC_DATA[22] LCDC_DATA[23] VIP_DATAIN[4] VIP_DATAIN[5] VIP_DATAIN[6] VIP_DATAIN[7] VIP_DATAIN[8] VIP_DATAIN[9] VIP_DATAIN[10] VIP_DATAIN[11] VIP_VSYNC VIP_HREF VIP_CLKIN GPIO1_B[4] SARADC_AIN[0] SARADC_AIN[1] SARADC_AIN[2] SARADC_AIN[3] VDDA_SARADC OTG0_VSSAC AC14 AD14 AA14 AB15 AC15 AD15 Y11 Y13 AA11 W14 W13 W12 W15 AB16 AC16 Y16 AB17 AD16 AA15 Y15 AB18 AC17 AD17 W16 AA23 Y23 Y24 AA24 AB24 W20 LCDC_DATA[12] LCDC_DATA[13] LCDC_DATA[14] LCDC_DATA[15] LCDC_DATA[16] LCDC_DATA[17] LCDC_DATA[18] LCDC_DATA[19] LCDC_DATA[20] LCDC_DATA[21] LCDC_DATA[22] LCDC_DATA[23] VIP_DATAIN[4] VIP_DATAIN[5] VIP_DATAIN[6] VIP_DATAIN[7] VIP_DATAIN[8] VIP_DATAIN[9] VIP_DATAIN[10] VIP_DATAIN[11] VIP_VSYNC VIP_HREF VIP_CLKIN GPIO1_B[4] SARADC_AIN[0] SARADC_AIN[1] SARADC_AIN[2] SARADC_AIN[3] 2.5V Analog Ground
Rev 1.0
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I/O A A A A AP AG 12 12 12 12 12 12 12 12 12 12 12 12 8 8 8 8 8 8 8 8 8 8 8 12 N/A N/A N/A N/A N/A N/A Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down N/A N/A N/A N/A N/A N/A I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down N/A N/A N/A N/A N/A N/A USB OTG2.0 SARADC Domain VDDIO_VIP ebc_sdce4 ebc_sdce5 ebc_border0 ebc_border1 ebc_gdpwr0 ebc_gdpwr1 ebc_gdpwr2 ebc_vcom ebc_sdshr ebc_gdoe ebc_gdsp ebc_gdrl vip_clkout Rockchips Confidential 36
RK2906-6 Datasheet
OTG0_DVSS OTG0_DVDD OTG0_VDD25 OTG0_DM OTG0_RKELVIN OTG0_DP OTG0_VSSA OTG0_VBUS OTG0_VDD33 OTG0_ID OTG1_ID OTG1_VDD33 OTG1_VSSA OTG1_DP OTG1_RKELVIN OTG1_DM OTG1_VDD25 OTG1_DVDD OTG1_DVSS OTG1_VSSAC VDDIO_UHOST USBHOST_DN USBHOST_DP VSSIO_UHOST VDDCORE_RTC VDDIO_RTC VDDIO_EFUSE EFUSE_VQPS VDDCORE_EFUSE FLASH_DATA[0] W21 V19 V22 V23 W24 V24 V21 W22 W23 V20 T20 U23 T21 T24 U24 T23 T22 U19 U21 U20 R22 R23 R24 R21 U18 P21 T19 R20 P20 N23 Digital Ground 1.2V 2.5V OTG0_DM OTG0_RKELVIN OTG0_DP Analog Ground OTG0_VBUS 3.3V OTG0_ID OTG1_ID 3.3V Analog Ground OTG1_DP OTG1_RKELVIN OTG1_DM 2.5V 1.2V Digital Ground Analog Ground 3.3V USBHOST_DN USBHOST_DP Digital Ground 1.2V 3.3V/1.8V 3.3V EFUSE_VQPS 1.2V FLASH_DATA[0]
Rev 1.0
DG DP AP A A A AG A AP A A AP AG A A A AP DP DG AG DP A A DG DP DP DP A DP I/O N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 8 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Down N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A I Down RTC Domain efuse Domain VDDIO_FLASH0 USB Host1.1 Domain USB Host2.0 Domain Domain Rockchips Confidential 37
RK2906-6 Datasheet
FLASH_DATA[1] FLASH_DATA[2] FLASH_DATA[3] FLASH_DATA[4] FLASH_DATA[5] FLASH_DATA[6] FLASH_DATA[7] FLASH_RDY FLASH_ALE FLASH_CLE FLASH_RDN FLASH_WRN FLASH_WP FLASH_CSN0 GPIO0_D[2] GPIO0_D[3] GPIO0_D[4] GPIO0_D[6] GPIO0_D[7] GPIO1_A[0] GPIO0_A[5] GPIO1_D[0] GPIO1_D[1] GPIO1_D[2] GPIO1_D[3] GPIO1_D[4] GPIO1_D[5] GPIO1_D[7] GPIO2_D[0] GPIO2_D[1] N19 L22 L23 N24 M23 L19 L21 N20 P19 M21 N21 K20 K19 M24 K24 K22 K23 J19 L24 J20 J21 D22 G20 D20 G22 B24 G19 E20 E24 H20 FLASH_DATA[1] FLASH_DATA[2] FLASH_DATA[3] FLASH_DATA[4] FLASH_DATA[5] FLASH_DATA[6] FLASH_DATA[7] FLASH_RDY FLASH_ALE FLASH_CLE FLASH_RDN FLASH_WRN FLASH_WP FLASH0_CSN GPIO0_D[2] GPIO0_D[3] GPIO0_D[4] GPIO0_D[6] GPIO0_D[7] GPIO1_A[0] GPIO0_A[5] GPIO1_D[0] GPIO1_D[1] GPIO1_D[2] GPIO1_D[3] GPIO1_D[4] GPIO1_D[5] GPIO1_D[7] GPIO2_D[0] GPIO2_D[1]
Rev 1.0
mddr_tq mii_rx_clkin mii_crs I/O I/O I/O I/O I/O I/O I/O I O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 12 8 8 8 8 8 8 12 8 Down Down Down Down Down Down Down Up Down Down Up Up Down Up Up Up Up Up Up Up Up Down Up Up Up Up Up Up Down Down I Down I Down I Down I Down I Down I Down I Down I Up O Down O Down O Up O Up O Down O Up I Up I Up I Up I Up I Up I Up I Up I Down I Up I Up I Up I Up I Up I Up I Down I Down VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO_FLASH1 flash_csn1 flash_csn2 flash_csn3 flash_csn5 flash_csn6 flash_csn7 flash_dqs sdmmc_clkout sdmmc_cmd sdmmc_data0 sdmmc_data1 sdmmc_data2 sdmmc_data3 sdmmc_data5 i2s0_clk i2s0_sclk Rockchips Confidential 38
RK2906-6 Datasheet
Rev 1.0
GPIO2_D[2] A21 GPIO2_D[2] i2s0_lrck_rx mii_tx_err I/O 8 Down I Down GPIO2_D[3] B22 GPIO2_D[3] i2s0_sdi mii_col I/O 8 Down I Down GPIO2_D[4] C21 GPIO2_D[4] i2s0_sdo0 mii_rxd2 I/O 8 Down I Down GPIO4_D[6] F20 GPIO4_D[6] i2s0_lrck_tx0 I/O 8 Down I Down GPIO5_A[3] B18 GPIO5_A[3] mii_tx_clkin I/O 8 Up I Up GPIO2_C[1] E14 GPIO2_C[1] spi0_csn0 I/O 8 Up I Up GPIO2_C[2] E15 GPIO2_C[2] spi0_txd I/O 8 Down I Down GPIO2_C[0] D14 GPIO2_C[0] spi0_clk I/O 12 Down I Down GPIO2_C[3] D15 GPIO2_C[3] spi0_rxd I/O 8 Down I Down GPIO2_C[4] F16 GPIO2_C[4] spi1_clk I/O 12 Down I Down GPIO2_C[5] A13 GPIO2_C[5] spi1_csn0 I/O 8 Up I Up GPIO2_C[6] B16 GPIO2_C[6] spi1_txd I/O 8 Down I Down GPIO2_C[7] C14 GPIO2_C[7] spi1_rxd I/O 8 Down I Down GPIO4_A[7] C15 GPIO4_A[7] spdif_tx I/O 8 Down I Down GPIO0_A[6] D18 GPIO0_A[6] mii_md I/O 8 Down I Down GPIO0_A[7] D11 GPIO0_A[7] mii_mdclk I/O 8 Down I Down GPIO5_D[7] F12 GPIO5_D[7] I/O 8 Up I Up GPIO6_D[0] V9 GPIO6_D[0] I/O 8 Down I Down GPIO6_D[1] W8 GPIO6_D[1] I/O 8 Down I Down GPIO6_D[2] V8 GPIO6_D[2] I/O 8 Down I Down GPIO6_D[3] W7 GPIO6_D[3] I/O 8 Down I Down GPIO6_C[0] C12 GPIO6_C[0] I/O 8 Down I Down GPIO6_C[1] E12 GPIO6_C[1] I/O 8 Down I Down GPIO6_C[2] A11 GPIO6_C[2] I/O 8 Down I Down GPIO6_C[3] D13 GPIO6_C[3] I/O 8 Down I Down GPIO6_C[4] F13 GPIO6_C[4] trace_data4 I/O 8 Down I Down GPIO6_C[5] E10 GPIO6_C[5] trace_data5 I/O 8 Down I Down GPIO6_C[6] C11 GPIO6_C[6] trace_data6 I/O 8 Down I Down GPIO6_C[7] E13 GPIO6_C[7] trace_data7 I/O 8 Down I Down GPIO1_A[6] A12 GPIO1_A[6] i2c1_sda I/O 8 Up I Up Rockchips Confidential 39
RK2906-6 Datasheet
GPIO1_A[7] GPIO4_A[5] GPIO4_A[6] GPIO4_D[0] GPIO4_D[1] GPIO4_D[2] GPIO4_D[3] GPIO4_D[4] GPIO4_D[5] GPIO1_A[3] GPIO1_A[5] GPIO1_B[5] GPIO2_A[2] GPIO2_A[3] GPIO2_A[4] GPIO2_A[5] GPIO2_B[6] GPIO2_B[7] GPIO5_D[3] GPIO5_D[4] GPIO6_B[5] GPIO6_B[6] GPIO6_B[7] GPIO5_D[2] GPIO5_D[5] GPIO5_D[6] GPIO3_A[0] GPIO3_A[1] GPIO3_A[2] GPIO3_A[3] B12 G17 B11 D12 E11 F10 F9 C10 F11 F15 A9 C8 B10 B9 C7 E9 C9 D10 B8 D9 B2 B1 A2 B7 A7 A6 D7 B6 C6 B5 GPIO1_A[7] GPIO4_A[5] GPIO4_A[6] GPIO4_D[0] GPIO4_D[1] GPIO4_D[2] GPIO4_D[3] GPIO4_D[4] GPIO4_D[5] GPIO1_A[3] GPIO1_A[5] GPIO1_B[5] GPIO2_A[2] GPIO2_A[3] GPIO2_A[4] GPIO2_A[5] GPIO2_B[6] GPIO2_B[7] GPIO5_D[3] GPIO5_D[4] GPIO6_B[5] GPIO6_B[6] GPIO6_B[7] GPIO5_D[2] GPIO5_D[5] GPIO5_D[6] GPIO3_A[0] GPIO3_A[1] GPIO3_A[2] GPIO3_A[3]
i2c1_scl
Rev 1.0
spi1_csn1 pwm3 pwm2 uart1_sir_in uart1_sir_out_n I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 12 8 8 8 Up Down Down Up Up Up Up Down Down Up Down Down Up Down Down Down Up Up Up Up Down Down Down Down Down Down Down Down Down Down I Up I Down I Down I Up I Up I Up I Up I Down I Down I Up I I Down I Up I Down I Down I Down I Up I Up I Up I Up I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down VDDIO_AP0 VDDIO_AP1 otg0_drv_vbus otg1_drv_vbus trace_data0 trace_data1 trace_data2 trace_data3 trace_clk trace_ctl emmc_detect_n emmc_pwr_en pwm0 sdmmc_detect_n sdmmc_write_prt uart1_sin uart1_sout i2c0_sda i2c0_scl i2c2_sda i2c2_scl pwm1 sdmmc_pwr_en sdio_pwr_en i2s1_clk i2s1_sclk i2s1_lrck_rx i2s1_sdi Rockchips Confidential 40
RK2906-6 Datasheet
GPIO3_A[4] GPIO3_A[5] GPIO2_A[6] GPIO2_A[7] GPIO2_B[0] GPIO2_B[1] GPIO2_B[2] GPIO2_B[3] GPIO2_B[4] GPIO2_B[5] GPIO1_B[6] GPIO1_B[7] GPIO1_C[0] GPIO1_C[1] GPIO6_A[0] GPIO6_A[1] GPIO6_A[2] GPIO6_A[3] GPIO6_A[4] GPIO6_A[5] GPIO6_A[6] GPIO6_A[7] GPIO6_B[0] GPIO6_B[1] GPIO6_B[2] GPIO6_B[3] GPIO6_B[4] GPIO5_A[0] GPIO5_A[1] GPIO5_A[2] A5 A4 C5 B4 E6 E8 A8 F8 D6 E7 D8 D5 A3 C4 A1 B3 C3 D4 E5 C1 D1 D2 E1 F1 E3 D3 C2 E2 F3 E4 GPIO3_A[4] GPIO3_A[5] GPIO2_A[6] GPIO2_A[7] GPIO2_B[0] GPIO2_B[1] GPIO2_B[2] GPIO2_B[3] GPIO2_B[4] GPIO2_B[5] GPIO1_B[6] GPIO1_B[7] GPIO1_C[0] GPIO1_C[1] GPIO6_A[0] GPIO6_A[1] GPIO6_A[2] GPIO6_A[3] GPIO6_A[4] GPIO6_A[5] GPIO6_A[6] GPIO6_A[7] GPIO6_B[0] GPIO6_B[1] GPIO6_B[2] GPIO6_B[3] GPIO6_B[4] GPIO5_A[0] GPIO5_A[1] GPIO5_A[2]
Rev 1.0
i2c3_sda i2c3_scl sdio_detect_n sdio_write_prt I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Down Down Up Up Down Down Down Down Up Up Down Down Up Up Down Down Down Down Down Down Down Down Down Down Down Down Down Up Up Up I Down I Down I Up I Up I Down I Down I Down I Down I Up I Up I Down I Down I Up I Up I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Down I Up I Up I Up i2s1_sdo i2s1_lrck_tx uart2_cts_n uart2_rts_n uart2_sin uart2_sout uart3_sin uart3_sout uart3_cts_n uart3_rts_n uart0_sin uart0_sout uart0_cts_n uart0_rts_n Rockchips Confidential 41
RK2906-6 Datasheet
GPIO0_A[0] GPIO0_A[1] GPIO0_A[2] GPIO0_A[3] GPIO0_A[4] GPIO4_A[0] GPIO4_A[1] GPIO4_A[2] GPIO4_A[3] GPIO4_A[4] NC0 NC1 NC2 NC3 NC4 NC5 NC6 F4 F2 G3 H3 G4 J1 J2 J3 H4 J4 U3 U4 AB3 AA4 AA8 AB8 W9 GPIO0_A[0] GPIO0_A[1] GPIO0_A[2] GPIO0_A[3] GPIO0_A[4] GPIO4_A[0] GPIO4_A[1] GPIO4_A[2] GPIO4_A[3] GPIO4_A[4] -- -- -- -- -- -- --
Rev 1.0
-- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O -- -- -- -- -- -- -- 8 8 8 8 8 8 8 8 8 8 -- -- -- -- -- -- -- Up Up Up Up Up Up Up Up Up Down -- -- -- -- -- -- -- I Up I Up I Up I Up I Up I Up I Up I Up I Up I Down -- -- -- -- -- -- -- -- -- -- -- -- -- -- Notes : Pad types : I = input , O = output , I/O = input/output (bidirectional) , AP = Analog Power , AG = Analog Ground DP = Digital Power , DG = Digital Ground A = Analog ② : Output Drive Unit is mA , only Digital IO have drive value ③①: : Reset state : I = input without any pull resistor , O = output without any pull resistor , I Up = input with weak pullup resistor , I Down = Input with weak pulldown resistor O Up =output with weak pullup resistor ,O Down =output with weak pulldown resistor ④: It is die location. For examples, “Left side” means that all the related IOs are always in left side of die : Power supply means that all the related IOs is in these IO power domain. If multiple powers is included, they are connected together in one IO power ring⑤Rockchips Confidential 42
RK2906-6 Datasheet 2.4
Rev 1.0
IO pin name descriptions
This sub-chapter will focus on the detailed function description of every pins based on different interface.
Table 2-4 RK2906-6 IO function description list Direction I Interface Pin Name EWAKEUP_STOP Description PMU stop mode dedicated external wakeup source PMU power down mode dedicated external wakeup source chip test mode enable chip boot device select (BootRom or Nor Flash) host interface bypass to lcdc interface enable Power on reset for chip Description sdmmc card clock. sdmmc card command output and reponse input. sdmmc card data input and output. sdmmc card detect signal, a 0 represents presence of card. sdmmc card write protect signal, a 1 represents write is protected. sdmmc card power-enable control signal EWAKEUP_POWER Misc TEST BTMODE LCDC_BYP NPOR I I I I I Direction O I/O I/O
Interface Pin Name sdmmc_clkout sdmmc_cmd sdmmc_datai SD/MMC Host Controller sdmmc_detect_n I (i=0~7) sdmmc_write_prt sdmmc_pwr_en I O
Interface CK CK_B CKEi (i=0,1) Pin Name Direction O O O Description Active-high clock signal to the memory device. Active-low clock signal to the memory device. Active-high clock enable signal to the memory device for two chip select. Active-low chip select signal to the memory device. AThere are two chip select. Active-low row address strobe to the memory device. Active-low column address strobe to the memory device. Active-low write enable strobe to the memory device. Bank address signal to the memory device. Address signal to the memory device. Bidirectional data line to the memory device. Active-high bidirectional data strobes to the memory device. Active-low bidirectional data strobes to the CS_Bi (i=0,1) O RAS_B O DMC CAS_B O WE_B BA[2:0] A[15:0] DQ[31:0] DQS[3:0] DQS_B[3:0] O O O I/O I/O I/O Rockchips Confidential 43
RK2906-6 Datasheet DM[3:0] O Rev 1.0 memory device. Active-low data mask signal to the memory device. On-Die Termination output signal for two chip select. Active-low retention latch enable input Reference Voltage input for three regions of DDR IO ZQ calibration pad which connects 240ohm±1% resistor LPDDR temperature output signal to DDR controller DLL digital test output. DLL analog test output. Description Interrupt signal from RK2906-6 to modem in indirect access mode. Host write enable signal in i80 interface and host enable signal in i68 interface Host read enable signal in i80 interface and host read/write indication in i68 interface Host chip select signal host address signal host data bus, host_data[15:0] is for host access , host_data[17:16] is only for lcd bypass Description Flash write-protected signal Flash address latch enable signal Flash command latch enable signal Flash write enable and clock signal Flash read enable and write/read signal Low 8bits of flash data inputs/outputs signal Flash data strobe signal Flash ready/busy signal Flash chip enable signal for chip 0 Flash chip enable signal for chip i, i=1~7 Description I2S/PCM0 clock source I2S/PCM0 serial clock I2S/PCM0 left & right channel signal for receiving serial data, synchronous left & right channel in I2S mode and the beginning of a group of left & right channels in PCM mode I2S/PCM0 serial data input ODTi (i=0,1) RET_EN VREFi (i=0,1,2) O I N/A ZQ_PIN N/A mddr_tq DLL_TEST_PIN[1:0] ANALOG_TEST_PIN I O N/A Direction O Interface Pin Name ap2bb_int host_wrn I HIF host_rdn host_csn host_addri (i=0,1) host_datai (i=0~17) I I I I/O Interface Pin Name IO_FLASH_WP IO_FLASH_ALE IO_FLASH_CLE IO_FLASH_WRN IO_FLASH_RDN NandC IO_FLASH_DATA[i](i=0~7) flash_dqs IO_FLASH_RDY IO_FLASH0_CSN flash_csni(i=1~7) Direction O O O O O I/O I/O I O O Direction O I/O I/O I Interface Pin Name i2s0_clk I2S/PCM0 Controller (8 channel) i2s0_sclk i2s0_lrck_rx i2s0_sdi Rockchips Confidential 44
RK2906-6 Datasheet i2s0_sdoi (i=0,1,2,3) i2s0_lrck_txi (i=0,1) O Rev 1.0 I2S/PCM0 serial data ouput I2S/PCM0 left & right channel signal for transmitting serial data, synchronous left & right channel in I2S mode (i=0) and the beginning of a group of left & right channels in PCM mode (i=0,1) Description I2S/PCM1 clock source I2S/PCM1 serial clock I2S/PCM1 left & right channel signal for receiving serial data, synchronous left & right channel in I2S mode and the beginning of a group of left & right channels in PCM mode I2S/PCM1 serial data input I2S/PCM1 serial data ouput I2S/PCM1 left & right channel signal for transmitting serial data, synchronous left & right channel in I2S mode and the beginning of a group of left & right channels in PCM mode I/O(i=0) O(i=1) Interface Pin Name i2s1_clk i2s1_sclk i2s1_lrck_rx i2s1_sdi i2s1_sdo i2s1_lrck_tx Direction O I/O I/O I O I/O I2S/PCM1 Controller (2 channel)
Interface SPDIF transmitter Pin Name spdif_tx Direction O Description spdif biphase data ouput
Interface Pin Name spix_clk (x=0,1) spix_csny SPI Controller (x=0,1) (y=0,1) spix_txd (x=0,1) spix_rxd (x=0,1) Direction I/O I/O O I spi serial clock spi chip select signal,low active spi serial data output spi serial data input Description
Interface Pin Name LCDC_DCLK Direction O Description LCDC RGB interface display clock out, MCU i80 interface RS signal LCDC RGB interface vertival sync pulse, MCU i80 interface CSN signal LCDC RGB interface horizontial sync pulse, MCU i80 interface WEN signal LCDC RGB interface data enable, MCU i80 interface REN signal LCDC data output/input LCDC_VSYNC LCDC O LCDC_HSYNC O LCDC_DEN LCDC_DATA[23:0] O I/O
Interface Pin Name VIP_CLKIN Camera IF vip_clkout VIP_VSYNC Direction I O I Description Camera interface input pixel clock Camera interface output work clock Camera interface vertical sync signal Rockchips Confidential 45
RK2906-6 Datasheet VIP_HREF VIP_DATAIN[11:4] I I Rev 1.0 Camera interface horizontial sync signal Camera interface high 8-bit input pixel data Description Pulse Width Modulation output Pulse Width Modulation output Pulse Width Modulation output Pulse Width Modulation output Interface Pin Name pwm3 PWM pwm2 pwm1 pwm0 Direction I/O I/O I/O I/O
Interface Pin Name i2c0_sda i2c0_scl i2c1_sda I2C i2c1_scl i2c2_sda i2c2_scl i2c3_sda i2c3_scl Direction I/O I/O I/O I/O I/O I/O I/O I/O I2C0 data I2C0 clock I2C1 data I2C1 clock I2C2 data I2C2 clock I2C3 data I2C3 clock Description
Interface Pin Name uart0_sin uart0_sout uart0_cts_n uart0_rts_n uart1_sir_out_n uart1_sin uart1_sout UART uart1_sir_in uart2_cts_n uart2_rts_n uart2_sin uart2_sout uart3_sin uart3_sout uart3_cts_n uart3_rts_n Direction I O I O O I O I I O I O I O I O Description UART0 searial data input UART0 searial data output UART0 clear to send UART0 request to send UART1 IRDA SIR data output UART1 searial data input UART1 searial data output UART1 IRDA SIR data input UART2 clear to send UART2 request to send UART2 searial data input UART2 searial data output UART3 searial data input UART3 searial data output UART3 clear to send UART3 request to send
Interface Pin Name OTG0_DM OTG0_RKELVIN USB OTG OTG0_DP OTG0_VBUS otg0_drv_vbus Direction N/A N/A N/A N/A O Description USB OTG 2.0 Data signal DM USB OTG 2.0 Transmitter Kelvin Connection to Resistor Tune Pin USB OTG 2.0 Data signal DP USB OTG 2.0 5-V power supply pin USB OTG 2.0 drive VBUS Rockchips Confidential 46
RK2906-6 Datasheet
Interface Pin Name OTG1_DM OTG1_RKELVIN OTG1_DP OTG1_VBUS otg1_drv_vbus
Rev 1.0
Direction N/A N/A N/A N/A O Description USB HOST 2.0 Data signal DM USB HOST 2.0 Transmitter Kelvin Connection to Resistor Tune Pin USB HOST 2.0 Data signal DP USB HOST 2.0 5-V power supply pin USB HOST 2.0 drive VBUS USB Host 2.0
Interface USB Host 1.1 Pin Name USBHOST_DN USBHOST_DP Direction N/A N/A Description UHOST DN data-line UHOST DP data-line
Interface SAR-ADC Pin Name SARADC_AIN[i] (i=0~3) Direction N/A Description SAR-ADC input signal for 4 channel
Interface eFuse Pin Name EFUSE_VQPS Direction N/A Description eFuse program and sense power
2.4.1
RK2906-6 IO Type The following list shows IO type except DDR IO and all of Power/Ground IO .
Table 2-5 RK2906-6 IO Type List Type Diagram Description Pin Name A B Analog IO Cell with IO voltage EFUSE_VQPS Dedicated Power supply to Internal Macro with IO voltage SARADC_AIN[3:0] C Crystal Oscillator with high enable XIN24M/XOUT24M Rockchips Confidential 47
RK2906-6 Datasheet Rev 1.0 Tri-state output pad with input, D limited slew rate and enable controlled pull-up Part of digital GPIO E Tri-state output pad with input, limited slew rate and enable controlled pull-down Part of digital GPIO Tri-state output pad with input, and enable controlled pull-up F Part of digital GPIO Tri-state output pad with input, and enable controlled pull-down G Part of digital GPIO
Rockchips Confidential 48
RK2906-6 Datasheet 2.5
Package information
Rev 1.0
RK2906-6 package is TFBGA512
(body: 16mm x 16mm ; ball size : 0.3mm ; ball pitch : 0.65mm)
2.5.1 Dimension
Fig. 2-2 RK2906-6 TFBGA512 Package Top View
Fig. 2-3 RK2906-6 TFBGA512 Package Side View
Rockchips Confidential 49
RK2906-6 Datasheet
Rev 1.0
Fig. 2-4 RK2906-6 TFBGA512 Package Bottom View
Fig. 2-5 RK2906-6 TFBGA512 Package Dimension
Rockchips Confidential 50
RK2906-6 Datasheet
Rev 1.0
Chapter 3 Electrical Specification 3.1
Absolute Maximum Ratings
Table 3-1 RK2906-6 absolute maximum ratings Parameters Related Power Group VDDCORE,VDDCORE_RTC, VDDCORE_EFUSE, OTG0_DVDD, OTG1_DVDD, DC supply voltage for Internal digital logic DVDD_APLL, DVDD_DPLL, DVDD_CGPLL VDDIO0~VDDIO6 VDDIO_LCD0, VDDIO_LCD1, VDDIO_VIP, VDDIO_SMC0, VDDIO_SMC1, VDDIO_FLASH0 , VDDIO_FLASH1, VDDIO_AP0, VDDIO_AP1, DC supply voltage for Digital GPIO (except for SAR-ADC, PLL, USB, DDR IO) DC supply voltage for DDR IO DC supply voltage for Analog part of SAR-ADC DC supply voltage for Analog part of PLL DC supply voltage for Analog part of USB OTG/Host2.0 Analog Input voltage for SAR-ADC Analog Input voltage for DP/DM/VBUS of USB OTG/Host2.0 Analog input voltage for RKELVIN/ID of USB OTG/Host2.0 Analog Input voltage for DP/DM of USB Host1.1 Digital input voltage for input buffer of GPIO Digital output voltage for output buffer of GPIO Storage Temperature VDDIO_UHOST, VDDIO_RTC, VDDIO_EFUSE VDDIO_DDR0~VDDIO_DDR6 VDDA_SARADC AHVDD_APLL AVDD_DPLL, AVDD_CGPLL OTG0_VDD25,OTG1_VDD25 OTG0_VDD33,OTG1_VDD33 1.95 2.75 2.75 1.32 2.75 3.63 2.75 5 2.75 3.6 3.6 3.6 150 V V V V V V V V V V ℃ 3.6 V 1.32 V Max Unit Absolute maximum ratings specify the values beyond which the device may be damaged permanently. Long-term exposure to absolute maximum ratings conditions may affect device reliability. 3.2
Recommended Operating Conditions Table 3-2 RK2906-6 recommended operating conditions Parameters VDDCORE, Symbol ①Min Typ Max Units Internal digital logic Power （except USB OTG) VDDCORE_RTC, VDDCORE_EFUSE, DVDD_APLL, DVDD_DPLL, DVDD_CGPLL 1.08 1.2 1.32 V USB Host1.1 IO Power VDDIO_UHOST 3 3.3 3.6 V Rockchips Confidential 51
RK2906-6 Datasheet
VDDIO0~VDDIO6 Digital GPIO Power(3.3V)
3 Rev 1.0
VDDIO_SMC0, VDDIO_SMC1 VDDIO_EFUSE VDDIO_LCD0, VDDIO_LCD1 VDDIO_VIP, VDDIO_RTC 3.3 3.6 V Digital GPIO Power(3.3V/1.8V) VDDIO_FLASH0 , VDDIO_FLASH1 VDDIO_AP0, VDDIO_AP1 3 1.62 3.3 1.8 3.6 1.98 V DDR IO (DDRII mode) Power DDR IO (DDRIII mode) Power DDR IO (LPDDR mode) Power DDR reference supply (VREF) Input DDR External termination voltage PLL(1.6GHz) Analog Power PLL(1.0GHz) Analog Power SAR-ADC Analog Power USB OTG/Host2.0 Digital Power USB OTG/Host2.0 Analog Power(2.5V) USB OTG/Host2.0 Analog Power(3.3V) USB OTG/Host2.0 external resistor PLL input clock frequency Operating Temperature VDDIO_DDR0~VDDIO_DDR6 VDDIO_DDR0~VDDIO_DDR6 VDDIO_DDR0~VDDIO_DDR6 VREF0,VREF1,VREF2 AHVDD_APLL AVDD_DPLL,AVDD_CGPLL VDDA_SARADC OTG0_DVDD, OTG1_DVDD OTG0_VDD25,OTG1_VDD25 1.7 1.425 1.65 0.49*VDDIO_DDR VREFi - 40mV (i =0~2) 2.25 1.08 2.25 1.116 2.325 1.8 1.5 1.8 0.5*VDDIO_DDR VREFi (i =0~2) 2.5 1.2 2.5 1.2 2.5 1.9 1.575 1.95 0.51*VDDIO_DDR VREFi + 40mV (i =0~2) 2.75 1.32 2.75 1.32 2.75 V V V V V V V V V V OTG0_VDD33,OTG1_VDD33 REXT 3.069 42.768 N/A -40 3.3 43.2 24 27 25 3.63 43.632 N/A 85 V Ohm MHz ℃ Notes : ①： Symbol name is same as the pin name in the io descriptions 3.3 DC Characteristics Table 3-3 RK2906-6 DC Characteristics Parameters Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Digital GPIO @3.3V Threshold Point Threshold Point with Pullup Resistor Enabled Threshold Point with Pulldown Resistor Enabled Pullup Resistor Pulldown Resistor Digital GPIO @1.8V Input Low Voltage Input High Voltage Vtpd Rpu Rpd Vil Vih Vtpu Symbol Vil Vih Vol Voh Vt Min -0.3 2 N/A 2.4 1.41 1.4 Typ 0 3.3 0 3.3 1. 1.52 Max 0.8 3.6 0.4 N/A 1.68 1.67 Units V V V V V V 1.42 34 35 -0.3 1.17 1.55 50 51 0 1.8 1.69 80 84 0.63 3.6 V Kohm Kohm V V Rockchips Confidential 52
RK2906-6 Datasheet
Output Low Voltage Output High Voltage Threshold Point Threshold Point with Pullup Resistor Enabled Threshold Point with Pulldown Resistor Enabled Pullup Resistor Pulldown Resistor Input High Voltage Input Low Voltage DDR IO @DDRIII mode Output High Voltage Output Low Voltage Input termination resistance(ODT) to VDDIO_DDRi/2 (i=0~6) Rtt Vtpd Rpu Rpd Vtpu Vol Voh Vt
N/A 1.35 0.8 0.79
Rev 1.0
0 1.8 0. 0.88 0.45 N/A 0.98 0.97 V V V V 0.8 60 VREF + 0.1 VSS-0.3 0.8*VDDQ 100 36 VREF i + 0.125 (i=0~2) 0. 111 106 120 60 40 0.98 204 202 VDDQ VREF - 0.1 0.2*VDDQ 140 66 44 VDDIO_DDRi + V Kohm Kohm V V V V Vih_ddr Vil_ddr Voh_ddr Vol_ddr Ohm Input High Voltage Vih_ddr 1.8 0.3 (i=0~6) V Input Low Voltage DDR IO @DDRII mode Output High Voltage Output Low Voltage Input termination resistance(ODT) to VDDIO_DDRi/2 (i=0~6) Input High Voltage Vil_ddr -0.3 VDDIO_DDRi - 0.28 (i=0~6) N/A 120 0 VREFi - 0.125 (i=0~2) N/A 0.28 180 90 60 N/A 0.3*VDDIO_DDRi (i=0~6) DVDD_iPLL (i=A,D,CG) 0.2*DVDD_iPLL (i=A,D,CG) N/A 0.8 V Voh_ddr Vol_ddr 1.8 0 150 75 50 1.8 V V Rtt 60 40 Ohm DDR IO @LPDDR mode Vih_ddr 0.7*VDDIO_DDRi (i=0~6) N/A 0.8*DVDD_iPLL (i=A,D,CG) 0 2 N/A V Input Low Voltage Vil_ddr 0 DVDD_iPLL (i=A,D,CG) 0 3.3 0 V Input High Voltage PLL Input Low Voltage USB Host1.1 IO Input High Voltage Input Low Voltage Vih_pll V Vil_pll Vih_uhost Vil_uhost V V V 3.4 Electrical Characteristics for General IO
Parameters Symbol Ii Ioz Iih Test condition Vin = 3.3V or 0V Vout = 3.3V or 0V Vin = 3.3V, pulldown disabled Min -10 -10 TBD Typ N/A N/A N/A Max 10 10 TBD Units uA uA uA Table 3-4 RK2906-6 Electrical Characteristics for Digital General IO Input leakage current Tri-state output leakage current High level input current Digital GPIO @3.3V Rockchips Confidential 53
RK2906-6 Datasheet
Rev 1.0
39 TBD 41 -10 -10 TBD 9 TBD 8.8 65 N/A 66 N/A N/A N/A 17 N/A 16 94 TBD 97 10 10 TBD 30 TBD 28 uA uA uA uA uA uA uA uA uA Vin = 3.3V, pulldown enabled Vin = 0V, pullup disabled Low level input current Input leakage current Tri-state output leakage current Digital GPIO @1.8V Low level input current High level input current Iih Vin = 1.8V, pulldown enabled Vin = 0V, pullup disabled Iil Vin = 0V, pullup enabled Iil Ii Ioz Vin = 0V, pullup enabled Vin = 1.8V or 0V Vout = 1.8V or 0V Vin = 1.8V, pulldown disabled 3.5 Electrical Characteristics for PLL Parameters Input clock frequency Comparison frequency VCO operating range Output clock frequency Lock time Symbol Fin Fref Fvco Fout Tlt N/A Test condition Fin = Fref * NR @2.5V/1.2V Fref = Fin/NR @2.5V/1.2V Fvco = Fref * NF @2.5V/1.2V Fout = Fvco/NO @2.5V/1.2V @ 2.5V/1.2V Fin = 50MHz, Fout = 1600MHz, @2.5V/1.2V, 25 ℃ BP=HIGH , PD= LOW , Fin = N/A 50MHz, Fout = 50MHz, @2.5V/1.2V, 25 ℃ N/A Fin Fref Fvco PD=HIGH, @2.75V/1.32V, 125 ℃ Fin = Fref * NR @1.2V Fref = Fin/NR @1.2V Fvco = Fref * NF @1.2V ①①①①①① Table 3-5 RK2906-6 Electrical Characteristics for PLL Min 10 10 800 100 N/A N/A Typ 24/27 N/A N/A N/A N/A 2.3 Max 400 50 1600 1600 0.2 N/A Units MHz MHz MHz MHz ms mW PLL(1.6G)②Power consumption (normal mode) Power consumption (bypass mode) Power consumption (power-down mode) Input clock frequency Comparison frequency VCO operating range(high-band) VCO operating range(low-band) Output clock frequency(high-band) Output clock frequency(low-band) N/A 85.6 N/A uW N/A 10 10 500 300 62.5 37.5 N/A N/A 1.36 24/27 N/A N/A N/A N/A N/A N/A 1.46 N/A 400 50 1000 600 1000 600 0.2 N/A uW MHz MHz MHz MHz MHz MHz ms mW Fout Tlt N/A Fout = Fvco/NO @1.2V @ 1.2V Fin = 50MHz, Fout = 1000MHz, High-band, @1.32V, 125 ℃ BP=HIGH , PD= LOW , Fin = PLL(1.0G)②Lock time Power consumption (normal mode) Power consumption (bypass mode) Power consumption (power-down mode) N/A 50MHz, Fout = 50MHz, @1.32V, 125 ℃ N/A 13.38 N/A uW N/A PD=HIGH, @1.32V, 125 ℃ N/A 1.41 N/A uW Notes : NR is the input divider value; NF is the feedback divider value; NO is the output divider value ②:
PLL(1.6G) is ARM PLL with AHVDD_APLL and DVDD_APLL power supply ;
Rockchips Confidential
①:
RK2906-6 Datasheet
Rev 1.0
PLL(1.0G) is DDR PLL/CODEC PLL/GENERAL PLL with AVDD_DPLL/AVDD_CGPLL and
DVDD_DPLL/DVDD_CGPLL power supply
3.6 Electrical Characteristics for SAR-ADC
Parameters Symbol Fs DNL INL Egain Eoffset Vin The duty cycle should be between 40%~60% Test condition Min N/A 0.1 N/A N/A -8 -8 N/A 0 N/A N/A N/A Typ 10 N/A ±1 ±2 N/A N/A 250 20 1 7 Max N/A 1 N/A N/A 8 8 N/A 1.5 N/A N/A N/A Units Bits MSPS LSB LSB LSB mV uA V uA uA 1/Fs Table 3-6 RK2906-6 Electrical Characteristics for SAR-ADC ADC resolution Conversion speed Differential Non Linearity Integral Nn Linearity Gain Error Offset Error Analog Supply Current(VDDA_SARADC) Input Voltage range Digital Supply Current Power Down Current Power up time 3.7 Electrical Characteristics for USB OTG/Host2.0 Interface Table 3-7 RK2906-6 Electrical Characteristics for USB OTG/Host2.0 Interface Parameters Test condition Min N/A N/A N/A N/A N/A N/A N/A N/A 75℃ , OTG0_VDD25 = OTG1_VDD25 = 2.5V, OTG0_VDD33 = OTG1_VDD33 = 3.3V, OTG0_DVDD = OTG1_DVDD = 1.2V , 15-cm USB cable attached to DP/DM N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Typ 4.11 2.68 22.7 3.98 2. 15 6.22 2.67 5.99 2.66 16.4 6.04 3.34 15.3 6.22 1.83 0.1 15.2 0.141 0.1 0.629 Max N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA uA uA uA mA uA mA HS transmit, maximum transition density (all 0's data in DP/DM) HS transmit, minimum transition density (all 1's data in DP/DM) Current From OTG_DVDD Current From OTG_VDD33 Current From OTG_VDD25 Current From OTG_DVDD Current From OTG_VDD33 Current From OTG_VDD25 Current From OTG_DVDD HS idle mode Current From OTG_VDD33 Current From OTG_VDD25 FS transmit, maximum transition density (all 0's data in DP/DM) LS transmit, maximum transition density (all 0's data in DP/DM) Current From OTG_DVDD Current From OTG_VDD33 Current From OTG_VDD25 Current From OTG_DVDD Current From OTG_VDD33 Current From OTG_VDD25 Current From OTG_DVDD Suspend mode Current From OTG_VDD33 Current From OTG_VDD25 Current From OTG_DVDD Sleep mode Current From OTG_VDD33 Current From OTG_VDD25 Rockchips Confidential 55
RK2906-6 Datasheet 3.8
Rev 1.0
Electrical Characteristics for USB Host1.1 Interface
Table 3-8 RK2906-6 Electrical Characteristics for USB Host1.1 Interface Parameters Symbol Pad to ground steady state drive Test condition Min N/A N/A N/A N/A N/A Typ 0.5 450 450 N/A 10 Max N/A N/A N/A 20 N/A Units uA uA uA pF Ohm FS current (standby mode) FS current (input mode) FS current (output mode) Transceiver pad capacitance Driver output resistance
3.9 Electrical Characteristics for DDR IO Parameters VDDIO_DDR standby Symbol Test condition @ 1.8V , 125℃ Min 0 Typ 0 Max 1.24 Units mA Table 3-9 RK2906-6 Electrical Characteristics for DDR IO DDR IO @DDRII mode current, ODT OFF Input leakage current, SSTL mode, unterminated Input leakage current @ 1.8V , 125℃ @ 1.8V , 125℃ @ 1.2V , 125℃ @ 1.8V , 125℃ 0 3.23 0.01 0 0 57.965 0.01 0 0.42 435.1 3.51 1.15 uA nA uA uA DDR IO @LPDDR mode VDD(1.2V) quiescent current VDDIO_DDR quiescent current
3.10 Electrical Characteristics for eFuse Table 3-10 RK2906-6 Electrical Characteristics for eFuse Parameters read current for VDDCORE_EFUSE(1.2V) read current for Active mode VDDCORE_EFUSE(1.2V) read current for EFUSE_VQPS read current for EFUSE_VQPS standby current for standby mode VDDCORE_EFUSE(1.2V) standby current for EFUSE_VQPS power-down current for power-down mode VDDCORE_EFUSE(1.2V) power-down current for EFUSE_VQPS Symbol Iload_vdd Test condition STROBE high normal read 10MHz STROBE high normal read 10MHz Min 3.12 Typ 4.78 Max 6.919 Units mA Iactive_vdd 1.88 2.791 4.016 mA Iload_vqps 0.004 0.014 0.365 uA Iactive_vqps 0.003 0.012 0.368 uA Istandby_vdd 0.032 0.21 39.852 uA Istandby_vqps 0.006 0.007 0.376 uA Ipd_vdd 0.005 0.031 4.679 uA Ipd_vqps 0.006 0.008 0.396 uA
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RK2906-6 Datasheet
Rev 1.0
Chapter 4 Hardware Guideline 4.1
Reference design for RK2906-6 oscillator PCB connection
Totally RK2906-6 may use three oscillators. Their typical clock frequency is 24MHz. The two oscillators with 24MHz will provide input clock to four on-chip PLLs, it is software-programmable to select one input clock from oscillator to PLLs .
External reference circuit for oscillators with 24MHz input
In the following diagram , the value for Rf,Rd,C1,C2 must be adjusted a little
to improve performance of oscillator based on real crystal model . Especially C1 and C2 value is advised to meet formula (C1 * C2)/(C1+C2) = ~8pF
Oscillator IOXIN24M/XIN27MXOUT24M/XOUT27MRf = 1M OhmRd = 0~200 Ohm8~12pF8~12pFFig. 4-1 External reference circuit for 24MHz oscillators
4.2 Reference design for PLL PCB connection The following reference design is suitable for two types of PLL in RK2906-6, one is ARM PLL with 1.6GHz, another is three PLLs with 1.0GHz, the difference is that they have different value for C1/C2/C3/C4 components, since these values are related with PLL VCO maximum oscillating frequency(Fvco) .
For 1.6GHz PLL, the AVDD/AVSS is mapped to AHVDD_APLL/AHVSS_APLL , DVDD/DVSS is mapped to DVDD_APLL/DVSS_APLL ;
For 1.0GHz PLLs , the AVDD/AVSS is mapped to AVDD_DPLL/AVSS_DPLL and AVDD_CGPLL/ AVSS_CGPLL, DVDD/DVSS is mapped to DVDD_DPLL/DVSS_DPLL and DVDD_CGPLL/DVSS_CGPLL.
Fig. 4-2 External reference circuit for PLL
In the above circuit, 1 Ohm resistor of the filter is recommended for loading PLL current based on IR drop consideration. For capacitors C1/C2/C3/C4 , SMD ceramic high-frequency capacitors are selected, and C1,C2,C3 must be chosen with the same series of product and dimension. Serial resonance frequency(SRF) of C1 is close to PLL Fvco (1.6GHz and 1.0GHz), after C1 value is decided , we can get C2/C3/C4 value based on the following formula : C2 = 2*C1
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RK2906-6 Datasheet
Rev 1.0
C3 = 2*C2
C4 = C_total – (C1+C2+C3)
Fc_filter = 1/(2*pi*R*C_total) < 100KHz
Another, please pay more attention to the following remindment :
Total parasitic inductance, including of wire bond+PCB trace length, should be as small as possible by using shorter bonding wire and PCB trace. All capacitors should be placed as close to power and GNC pins as possible and shorten the current loop as short as possible.
Use wide traces for power and ground paths.Keep adjacent digital signals and power traces away from AVDD/AVSS to avoid coupling noise.
4.3 Reference design for USB OTG/Host2.0 connection
In RK2906-6 there are USB OTG and USB Host2.0 interface, in fact, same interface is for them.The following diagram shows external reference design . Of course, for USB Host2.0 some signals can be removed based on different application.
Fig. 4-3 RK2906-6 USB OTG/Host2.0 interface reference connection REXT
4.4 RK2906-6 Power up/down sequence requirement For all of the power supply in RK2906-6, there is no any specific requirement of power up/down sequence except power supply between core logic and DDRII/LPDDR IO or digital GPIO , between USB OTG/Host2.0 power supply .
Power supply sequence for core logic(VDDCORE) and DDRII/LPDDR IO (VDDIO_DDRi) (i=0~6)
It is generally recommended that the VDDCORE and VDDIO_DDRi be
powered-up together, and it is also acceptable for VDDCORE supply to power-up a very short time before the VDDIO_DDRi supply. If VDDIO_DDRi supply must power-up before the
VDDCORE supply, it is advised to keep the time between these two events less than 100ms to limit excessive VDDIO_DDRi current draws.
①
Power supply sequence for core logic(VDDCORE) and digital GPIO power
It is generally recommended that “turn on the higher GPIO voltage first and then the lower core voltage” so that the crowbar current would not occur on the power-up stage. Also it is acceptable that “turn on the lower core voltage first and then
higher GPIO voltage” only if the GPIO control pins are set to a fixed state. However, the ramp-up time for them can not be less than 10us.
There is no requirement on the power-down sequence for two above groups. Customers can decide which voltage to be down first based on the application need.
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RK2906-6 Datasheet
Rev 1.0
Power supply sequence for USB OTG/Host2.0
Please follow the following sequence for power up and recommended ramp-up time is more than 10us
OTGi_DVDD (1.2V)->OTGi_VDD25 (2.5V)->OTGi_VDD33 (3.3V) (i=0,1) For power down sequence , just reverse with power up sequence .
OTGi_VDD33 (3.3V)->OTGi_VDD25 (2.5V)->OTGi_DVDD (1.2V) (i=0,1) ①:
Notes :digital GPIO power include VDDIOi (i=0~6) , VDDIO_VIP, VDDIO_RTC, VDDIO_EFUSE, VDDIO_UHOST , VDDIO_LCDCj, VDDIO_FLASHj, VDDIO_SMCj , VDDIO_APj (j=0~1) .
4.5 RK2906-6 Power on reset descriptions
The following figure shows power-on-reset sequence. External power-on-reset input signal NPOR is released after stabilization of oscillator input clock XIN24M. Internal signal sysrstn is generated after NPOR is filtered glitch , which can filter out 5 clock cycles(24MHz) for low pulse of NPOR, so 208ns or 185ns low pulse of NPOR will not be recognized as valid power-on-reset signal for RK2906-6. To make PLLs work normally, the internal power down signal(pllpd) for PLLs must be high after power-on-reset, and maintains high level for more than 1us after sysrstn is deasserted. After pllpd is deasserted, PLLs will consume up to 200us to lock. So the system will wait about 208us, then deactive internal reset signal chiprstn, which is used to control generation logic of all the clock inside CRU. After 256 cycles or about 10.7us , rstn_pre for reset signal of all internal IPs will be deasserted , in other words, about 10.7us of clock has been generated before reset of every internal module is released.
NPORsysrstnpllpdchiprstnrstn_pre(IP reset)1.2us208us10.7usFig. 4-4 RK2906-6 reset signals sequence Rockchips Confidential 59
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