MEMORY存储芯片TMS320TCI100BCLZ6中文规格书

SPRS377F–SEPTEMBER2008–REVISEDJUNE2014

Table6-66.Additional(1)SPI1MasterTimings,5-PinOption(2)

No.

PARAMATER

Polarity=0,Phase=0,fromSPI1_CLKfalling

Maxdelayforslaveto

deassertSPI1_ENAafterfinalSPI1_CLKedgetoensuremasterdoesnotbeginthenexttransfer.(4)

Polarity=0,Phase=1,fromSPI1_CLKfallingPolarity=1,Phase=0,fromSPI1_CLKrisingPolarity=1,Phase=1,fromSPI1_CLKrisingPolarity=0,Phase=0,fromSPI1_CLKfalling

DelayfromfinalSPI1_CLKedgeto

masterdeassertingSPI1_SCS(5)(6)

Polarity=0,Phase=1,fromSPI1_CLKfallingPolarity=1,Phase=0,fromSPI1_CLKrisingPolarity=1,Phase=1,fromSPI1_CLKrising

21

td(SCSL_ENAL)M

MaxdelayforslaveSPItodriveSPI1_ENAvalidaftermasterassertsSPI1_SCStodelaythemasterfrombeginningthenexttransfer,

Polarity=0,Phase=0,toSPI1_CLKrising

DelayfromSPI1_SCSactivetofirstSPI1_CLK(7)(8)(9)

Polarity=0,Phase=1,toSPI1_CLKrisingPolarity=1,Phase=0,toSPI1_CLKfallingPolarity=1,Phase=1,toSPI1_CLKfallingPolarity=0,Phase=0,toSPI1_CLKrising

DelayfromassertionofSPI1_ENAlowtofirstSPI1_CLKedge.(10)

Polarity=0,Phase=1,toSPI1_CLKrisingPolarity=1,Phase=0,toSPI1_CLKfallingPolarity=1,Phase=1,toSPI1_CLKfalling

(1)(2)(3)(4)(5)

2P-5

0.5tc(SPC)M+2P-50.5tc(SPC)M+P-3

P-3

MIN

(3)

MAX0.5tc(SPC)M+P+5

P+5

UNIT

18

td(SPC_ENA)M

ns

0.5tc(SPC)M+P+5

P+5

20

td(SPC_SCS)M

ns

0.5tc(SPC)M+P-3

P-3

C2TDELAY+P

ns

22

td(SCS_SPC)M

ns

2P-5

0.5tc(SPC)M+2P-5

3P+3

0.5tc(SPC)M+3P+3

ns

3P+3

0.5tc(SPC)M+3P+3

23

td(ENA_SPC)M

TheseparametersareinadditiontothegeneraltimingsforSPImastermodes(Table6-63).P=SYSCLK2period

FigureshowsonlyPolarity=0,Phase=0asanexample.Tablegivesparametersforallfourmasterclockingmodes.InthecasewherethemasterSPIisreadywithnewdatabeforeSPI1_ENAdeassertion.

ExceptformodeswhenSPIDAT1.CSHOLDisenabledandthereisadditionaldatatotransmit.Inthiscase,SPI1_SCSwillremainasserted.

(6)ThisdelaycanbeincreasedundersoftwarecontrolbytheregisterbitfieldSPIDELAY.T2CDELAY[4:0].(7)IfSPI1_ENAisassertedimmediatelysuchthatthetransmissionisnotdelayedbySPI1_ENA.(8)InthecasewherethemasterSPIisreadywithnewdatabeforeSPI1_SCSassertion.

(9)ThisdelaycanbeincreasedundersoftwarecontrolbytheregisterbitfieldSPIDELAY.C2TDELAY[4:0].(10)IfSPI1_ENAwasinitiallydeassertedhighandSPI1_CLKisdelayed.

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SPRS377F–SEPTEMBER2008–REVISEDJUNE2014

SYNCInSYNCOutSYNCCTRPHS(phase register−32 bit)TSCTR(counter−32 bit)OVFRST32CTR [0−31]32PRD [0−31]CTR_OVFDelta−modeAPWM modeCTR [0−31]PRD [0−31]CMP[0−31]CTR=PRDCTR=CMPPWMcomparelogic32CAP1(APRD active)APRDshadow3232LDLD1PolarityselectCMP[0−31]32CAP2(ACMPactive)32LDLD2PolarityselectEventqualifierEventPre-scalePolarityselectACMPshadow32CAP3(APRD shadow)LDLD332CAP4(ACMPshadow)LDLD4Polarityselect44Capture eventsCEVT[1:4]InterruptTriggerandFlagcontrolto InterruptControllerCTR_OVFCTR=PRDCTR=CMPContinuous /OneshotCapture ControlFigure6-42.eCAPFunctionalBlockDiagram

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MODE SELECTeCAPx