Voltage booster circuit

专利名称：Voltage booster circuit发明人：Arakawa, Hideki申请号：EP94104235.0申请日：19940317公开号：EP0616329B1公开日：19980923

摘要：A booster circuit which can cancel the back bias effect, can prevent the increaseof the surface area of the circuit and the power consumption, prevent the complication ofthe clock generation circuit, and prevent lowering of the current capability, wherein aboosting stage is constituted by forming an nMOS transistor NT for carrying the chargesand nMOS transistor NTB for transferring the voltage inside a p-well formed inside an n-well which is formed on a p-type semiconductor substrate and biased to a predeterminedpotential, constituted so that the source voltage of the nMOS transistor NT for carryingthe charges which rise at the boosting is transferred via the nMOS transistor NTB fortransferring the voltage to the substrate, that is, the p-well, whereby the back bias effectis suppressed.

申请人：SONY CORP

地址：JP

国籍：JP

代理机构：Müller, Frithjof E., Dipl.-Ing.

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