Data packing circuit and data packing method

专利名称：Data packing circuit and data packing

method

发明人：Ying-Ying Song,Chien-Hsun Lu,Yi-Han

Peng,Chun-Chieh Chan

申请号：US17083445申请日：20201029公开号：US11137971B2公开日：20211005

专利附图：

摘要：A data packing circuit and a data packing method operated in a high definitionmultimedia interface (HDMI) transmitter that adopts a fixed rate link mode are provided.

The data packing circuit can output a plurality of FRL super blocks at a plurality of unittimes. In the data packing method, multiple valid data inputted to the data packing circuitat the (i)unit time are mapped to a plurality of FRL characters, and the FRL characters arestored to the first or the second buffer. At the same time, an amount of tri-byte of themultiple valid data is counted for determining number and positions for inserting gapcharacters to form the (i)FRL super block, which is outputted at the (i+1)unit time. Thenumeral ‘i’ is a positive integer.

申请人：REALTEK SEMICONDUCTOR CORP.

地址：Hsinchu TW

国籍：TW

代理机构：Li & Cai Intellectual Property (USA) Office

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