oc8051_design

www.opencores.org 8051 Core 8/10/2002

oc8051 Design

Document

Authors: Jaka Simsic

Simon Teran

**********************.uni-lj.si **********************.uni-lj.si

Rev. 0.2

October 8. 2002

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Revision History

Rev. 0.1 0.2 Date Authors 02/09/02 Jaka Simsic, Simon Teran 08/10/02 Jaka Simsic, Description First Draft Verification added Simon Teran www.opencores.org Rev 0.2

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Contents

1. About 8051 ............................................................................................................................. 7 1.1. Architecture Overwiev ........................................................................................................ 7 1.1.2. Memory Organization .................................................................................................. 8 1.1.3. Special Function Registers (SFRs) ............................................................................. 10 1.1.4. Addressing Modes ...................................................................................................... 11 1.1.5. Machine Cycles .......................................................................................................... 11 1.2. oc8051 ............................................................................................................................... 11 1.2.1. Directory structure ...................................................................................................... 12 2. oc8051 Realization ............................................................................................................... 13 2.1. oc8051 Plan ....................................................................................................................... 13 2.2. Program Memory and SFRs .............................................................................................. 15 2.3. Module Hierarchy ............................................................................................................. 15 2.4. Concept ............................................................................................................................. 16 2.5. Module Descriptions ......................................................................................................... 17 2.5.1. oc8051_top ................................................................................................................. 17 2.5.2. oc8051_decoder ......................................................................................................... 17 Output signals ................................................................................................................... 18 2.5.3. oc8051_alu ................................................................................................................. 18 2.5.4. oc8051_pc .................................................................................................................. 19 2.5.5. oc8051_rom ................................................................................................................ 19 2.5.6. oc8051_comp ............................................................................................................. 19 2.5.7. oc8051_op_select ....................................................................................................... 20 2.5.8. oc8051_regX .............................................................................................................. 20 2.6. Data Memory and SFRs .................................................................................................... 20 2.6.1. oc8051_ram_top ......................................................................................................... 21 2.6.2. oc8051_acc ................................................................................................................. 21 2.6.3. oc8051_b_register ...................................................................................................... 21 2.6.4. oc8051_psw ................................................................................................................ 21 2.6.5. oc8051_dptr ................................................................................................................ 21 2.6.6. oc8051_sp ................................................................................................................... 22 2.6.7. oc8051_ports .............................................................................................................. 22 2.6.8. oc8051_tc ................................................................................................................... 22 2.6.9. oc8051_int .................................................................................................................. 23 2.6.10. oc8051_uart .............................................................................................................. 24 2.6.11. oc8051_indi_addr ..................................................................................................... 25 2.6.12. oc8051_ram_sel ....................................................................................................... 25 2.7. Multipleksers ..................................................................................................................... 25 2.7.1. oc8051_alu_src1_sel .................................................................................................. 25 2.7.2. oc8051_alu_src2_sel .................................................................................................. 25 2.7.3. oc8051_alu_src3_sel .................................................................................................. 25 2.7.4. oc8051_cy_select ....................................................................................................... 25 2.7.5. oc8051_ext_addr_sel .................................................................................................. 26 2.7.6. oc8051_immediate_sel ............................................................................................... 26 2.7.7. oc8051_ram_rd_sel .................................................................................................... 26 2.7.8. oc8051_ram_wr_sel ................................................................................................... 26 www.opencores.org

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2.7.9. oc8051_rom_addr_sel ................................................................................................ 26 2.8. Instruction execution ......................................................................................................... 26 2.8.1. Arithmetic and logic instructions ............................................................................... 27 2.8.2. Data transfer instructions ........................................................................................... 28 2.8.3. Bit addressable instructions ........................................................................................ 29 2.8.4. Program jumps ........................................................................................................... 30 2.8.5. Addressing modes ...................................................................................................... 30 2.9. Interrupts ........................................................................................................................... 32 3. Verification .......................................................................................................................... 33 3.1. Additional modules ........................................................................................................... 33 3.1.1. oc8051_tb ................................................................................................................... 33 3.1.2. oc8051_xram .............................................................................................................. 33 3.1.3. oc8051_uart_test ........................................................................................................ 33 3.2. Features ............................................................................................................................. 33 3.3. Port p3 ............................................................................................................................... 33 3.4. Programs ........................................................................................................................... 34

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Table of Figures

Figure 1 Interfae ......................................................................................................................... 7 Figure 2 Program memory ......................................................................................................... 9 Figure 3 Lower part of program memory ................................................................................... 9 Figure 4 Data memory .............................................................................................................. 10 Figure 5 Design diagram .......................................................................................................... 14 Figure 6 Memory design diagram ............................................................................................ 15 Figure 7 Program status word (PSW) ...................................................................................... 21 Figure 8 Timer mode register (TMOD) ................................................................................... 22 Figure 9 Timer control register (TCON) .................................................................................. 23 Figure 10 Interrupt enable register (IE) .................................................................................... 23 Figure 11 Interrupt priority register (IP) .................................................................................. 24 Figure 12 Serial control register (SCON) ................................................................................ 24 Figure 13 Instruction execution ................................................................................................ 27 Figure 14 External rom access ................................................................................................ 28 Figure 15 Bit addressable instruction ....................................................................................... 29 Figure 16 Addressing internal ram ........................................................................................... 32 Figure 17 Interrupts .................................................................................................................. 32 Figure 18 Verification .............................................................................................................. 34

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1

About 8051

The 8051 microcontroller is member of MCS-51 family, originally designed in the 1980's by Intel. The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedded system products.

1.1. Architecture Overwiev

Microcontroller features are 8-bit CPU, on-chip memory (some of which is read-only), two 16-bit timer/counters and four 8-bit I/O ports.

Interface rstclkint0int1t0t1txdrxdearom_addrop1op2op3oc8051p0_outp1_outp2_outp3_outp0_inp1_inp2_inp3_inadd_owe_ostb_ocyc_oack_idat_odat_i Figure 1 Interfae

Pin description name rst clk int0 int1 direction size input input input input description 1 reset 1 clock 1 external interrupt 0 1 external interrupt 1 interrupt interface timer/counter inputs www.opencores.org Rev 0.2 7 of 34

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t0 t1 rxd txd ea rom_addr op1 op2 op3 adr_o stb_o cyc_o ack_I dat_I dat_o p0_in p1_in p2_in p3_in p0_out p1_out p2_out p3_out input input input output input output input input input output output output input input output 8 8 8 8 8 8 8 8 input input input input output output output output 8051 Core

1 timer 0 input 1 timer 0 input 1 receive 1 transmit 1 16 8 8 8 16 1 1 1 8 8 external access rom address operation 1 input operation 2 input operation 3 input address strobe cyrcle acknowlege data input data output port 0 input port 1 input port 2 input port 3 input port 0 output port 1 output port 2 output port 3 output 8/10/2002

serial interface interface to external program rom interface to external data ram port interface

1.1.2. Memory Organization

8051 has separated Data and Program Memory.

Program Memory is read-only. There is 64K bytes of Program Memory and up to 4K bytes of on-chip Program Memory (in later versions up to 8K or 16K of on-chip Program Memory). Remaining part of the Program Memory is external and can be reached with EA signal.

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exernal programrom2^INT_ROM_WIDexernal programromea = 00000hinteranl programromea = 1 Figure 2 Program memory

After reset and interrupts 8051 jumps to fixed address. Figure 3 shows a map of the lower part of the program memory. serial port interrupt vectortimer 1 overflow interrupt vectorexternal interrupt vector 1timer 0 overflow interrupt vectorexternal interrupt vector 0reset vector0023h0018h0013h0008h0003h0000h Figure 3 Lower part of program memory

The memory architecture of 8051 core includes 128 bytes of on-chip Data Memory which are more easily accessible directly by its instructions and there is also a number of Special Function Registers (SFRs). 8052 version has 256 bytes of on-chip Data Memory, but the upper 128 bytes are accesable only with indirect addressing. Direct addressing is used for accessing lower portion of Data Memory and SFRs. Internal Data Memory is divided to four banks of eight registers and to a special 32-byte long segment which is bit addressable.

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exernal data ramffhinternal data ram00h0000h Figure 4 Data memory

1.1.3. Special Function Registers (SFRs)

In this group you can find special registers, witch can be foun in internal ram in addresses from 80h to ffh.

f8h f0h e8h e0h d8h d0h c8h c0h b8h b0h a8h a0h 98h 90h 88h 80h b acc psw ip p3 ie p2 scon p1 tcon p0 sbuf tmod sp tl0 dpl tl1 dph th0 th1 pcon ffh f7h efh e7h dfh d7h cfh c7h bfh b7h afh a7h 9fh 97h 8fh 87h

- Accumulator (ACC)

Intended for use by special instructions. - B register

Used at multiplying and dividing.

- Status register (program status word, PSW) Contains program status information. - Stack pointer (SP)

Used with PUSH and POP istructions and in jump to/from subroutines. Reset sets it to 07h. -Data pointer (DPTR) www.opencores.org

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DPTR is composed from upper byte (DPH) and lower byte (DPL). This is neccesary to accomplish 16 bit address. - Pors 0 to 3

Four 8 bit I/O ports, used for interaction brtween microcontroller and ist environment. - two 16 bit Timer/Counters

Each is built from two 8 bit registers (TH0, TL0, TH1, TL1). - Control registers

Registers for controlling the rest of perifery (interrupts, timers…)

1.1.4. Addressing Modes

- direct addressing (Data Memory and SFRs)

In direct addressing the operand is specified by an 8-bit address field in the instruction. This address mode is possible only for addressing internal Data RAM and SFRs. - indirect addressing

In indirect addressing the instruction specifies a register which contains the address of the operand. The address register for 8-bit addresses can be R0 or R1 of the selected register bank, or the Stack Pointer. The address register for 16-bit addresses can only be the 16-bit “data pointer” register, DPTR.

Both internal and external RAM can be indirectly addressed. - register instructions

Special instructions are used for accessing four register banks (containing registers R0 to R7). This instructions have a 3-bit register specification within the opcode of the instruction. Register bank is selected by two bank select bits in PSW. - register- specific instructions

These are instructions which are specific to a certain register and they don't need an address byte (they always operate with the same register). The most common are those that use ACC register.

- immediate constants

In this address mode the value of a constant follows the opcode. - indexed addressing

In this mode only Program Memory can be accessed. The address wanted is sum of 16 bit base register (DPTR or PC) and accumulator (ACC).

1.1.5. Machine Cycles

Each machine cycle in 8051 is composed from six stages. Every stage lasts for two clock periods. That means every istruction needs at least twelve clock periods, some of them need even two machine cycles or more (multiplying, dividing…).

1.2. oc8051

Oc8051 has all properties of its Intel predecessor, with few exceptions:

- it has two stage pipeline, so all instructions (except jumps) can be executed in one clock period

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- there is 256 bytes of on-chip Data Memory, SFRs and general-purpose memory share same address space

- 64K of on-chip Program Memory

- there are separate connection for input and output ports and every special function (address for external memory, data bus, interrupts) has its own pin (at 8051 these are realized like special port functions)

1.2.1. Directory structure

• oc8051

o asm

▪ hex ▪ in ▪ v ▪

vec o bench

▪

verilog o doc

▪ pdf ▪

src o rtl

▪

verilog

o sim

▪

rtl_sim

• out • run • src

o verilog

o sw

▪ source

o syn

▪ src

• verilog

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2

oc8051 Realization

2.1. oc8051 Plan

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oc8051_alu_src1_seloc8051_alu_src2_seloc8051_alu_src3_seloc8051_cy_selectoc8051_compoc8051_aluoc8051_multiplyoc8051_divideoc8051_decoderoc8051_ram_rd_selRom & SFRoc8051_ram_wr_seloc8051_immedate_seloc8051_op_selectoc8051_pcoc8051_romoc8051_rom_addr_sel Figure 5 Design diagram

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2.2. Program Memory and SFRs

oc8051_ram_selread addres from oc8051_rom_ad_selto alu source selectoc8051_accoc8051_b_registerpsw outputs (carry,overflow...)from decoderto ram write and readselectrxdtxdie0ie1t0t1oc8051_intoc8051_pswoc8051_ram_topoc8051_spoc8051_ramoc8051_uartoc8051_tcoc8051_dptroc8051_indi_addroc8051_ext_addr_seldestination 1 from oc8051_alu,write address fromoc8051_ram_wr_sel, writefroom oc8051_decoder.Exteranl ram Figure 6 Memory design diagram

2.3. Module Hierarchy

oc8051_top

o oc8051_decoder www.opencores.org

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o oc8051_alu

▪ oc8051_divide ▪ oc8051_multiply o oc8051_alu_src1_sel o oc8051_alu_src2_sel o oc8051_alu_src3_sel o oc8051_comp o oc8051_cy_select

o oc8051_immediate_sel o oc8051_op_select o oc8051_pc

o oc8051_ram_rd_sel o oc8051_ram_wr_sel o oc8051_rom_addr_sel o oc8051_ram_top

▪ oc8051_ram o oc8051_ram_sel o oc8051_acc

o oc8051_b_register o oc8051_dptr

o oc8051_ext_addr_sel o oc8051_indi_addr o oc8051_ports o oc8051_psw o oc8051_sp o oc8051_int o oc8051_tc o oc8051_uart

8051 Core 8/10/2002

2.4. Concept

Oc8051 is compatible with 8051 microcontroller and with its perifery. With compatible we mean that oc8051 uses the same instruction set. There are of course quite a few differences in realization itself.

First and maybe the most important difference is pipeline with two stages. In first period instruction and its operands are fetched and decoded, second period is used for computing the result and writing it to the memory. We achieve this with additional set of registers which only task is to delay signals for one clock period. This is a must because the idea is that we set all control signals already in the first period and then delay the one that are not needed (for example, address where the result will be saved) for one period.

Because we might also need the second and third byte of the instruction we use Program ROM with 24 bits wide bus. Because of processor design we also use inner memory which is capable to simultaneously write and read.

One of important aspects is also bus control, which is handled by main module (oc8051_decoder). We achieve this with control signals which are connected to multipleksers that are set at the beginning of each bus. With multipleksers we set who controls the bus at the moment.

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2.5. Module Descriptions

2.5.1. oc8051_top

Module oc8051_top is at the top of module hierarchy and represents interface with the environment. It does not contain any 'always' commands and is only used for interaction between modules and environment.

Ports: - rst reset - clk clock

- rom_addr Program Memory address - rom_data Program Memory data - ea external access: is used when the external memory is accesed

- int0 external interrupt 0 - int1 external interrupt 1

- dat_i input for external Data Memory - dat_o output for external Data Memory - adr_o external Data Memory address - we_o writing to external Data Memory - stb_o strobe - ack_i acknowlage - cyc_o cycle

- p0_in, p1_in, p2_in, p3_in port inputs - p0_out, p1_out, p2_out, p3_out port outputs

- op1, op2, op3 inputs from external Program Memory (3x 8 bitov)

- rxd - txd - t0, t1

receive transmit

t/c external inputs

2.5.2. oc8051_decoder

As it was already mentioned oc8051_decoder is main module. This module gets operation code from the Program Memory and then sets control signals.

There are two internal signals. First is two bit wide signal, state. This signal obviously holds information about the state, that is the state of the pipeline. Typical value for this signal is b00. This value is changed only when the execution of command in the pipeline is blocked (jumps …). Second internal signal is op, this is registers in which we save operation code and is also needed only with instructions that take more then one clock period to complete (jumps again).

Module is composed from five 'always' commands:

- first and longest contains 'case' sentence in which we get information in which state is pipeline. With that information and with information about operation code we set control signals.

- second 'always' is for remembering operation code - third is for setting signal state to desired value www.opencores.org

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- forth 'always' takes care for output signal reti - and last 'always' command is for signal write_x

Output signals

- - - - - - - - - - - - - - - - - - - -

- - -

ram_rd_sel defines the source of the read address ram_wr_sel defines the source of the write address wr is set when we write to the memory src_sel1 defines the source for first ALU input src_sel2 defines the source for second ALU input src_sel3 defines the source for third ALU input alu_op defines ALU operation psw_set defines which flags in PSW register are set cy_sel carry select comp_sel compare byte select (is useful for conditional jumps) bit_addr is set when istruction is bit addressable wad2 defines if the second output from ALU is written to ACC (instructions mul and div) imm_sel immediate operand selection pc_wr is set when we change program counter (PC) pc_sel PC select – defines the address for new PC value rom_addr_sel defines source for Program Memory address ext_addr_sel defines source for external Data Memory address rd ready (0 normal activities, 1 pipeline stop) wr_xaddr write to external Data Memory (active high) reti return from interrupt rmw if active we have read-modify-write instruction (details are at port descriptions)

we_o stb_o

write to external ram strobe to external ram

2.5.3. oc8051_alu

Module oc8051_alu represents combinational logic for arithmetical and logical operations. Module has three 8 bit input operands (third operand is needed only for computing the address for PC or DPTR) and three input signals. This three signals are carry, auxiliary carry and a signal which is used for bit addressable instructions. And there is also four bits wide input for operation code.

Next operations are available:

• OC8051_ALU_NOP – no operation • OC8051_ALU_ADD - adding • OC8051_ALU_SUB - substracting • OC8051_ALU_MUL - multiplying • OC8051_ALU_DIV - dividing

• OC8051_ALU_DA – decimal adjust

• OC8051_ALU_NOT – negation, bit negation • OC8051_ALU_AND – and, bit and • OC8051_ALU_XOR – exclusive or • OC8051_ALU_OR - or www.opencores.org

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OC8051_ALU_RL – rotacion left

OC8051_ALU_RLC – rotacion left with carry (operation swap nibbles) OC8051_ALU_RR – rotacion right

OC8051_ALU_RRC – rotacion right with carry

OC8051_ALU_PCS – adding 16 bit unsigned number with 8 bit signed number (tows-complement)

• OC8051_ALU_XCH – excange, first input is transfered to second output and vice versa. If carry is set only lowest halfs of bytes are changed

Exact coding of operations is written in oc8051_defines.v file.

Output from module are two 8 bit results, carry, auxiliary carry and overflow.

For multiplying and dividing submodules oc8051_multiply and oc8051_divide are used. They both have 8 bit input bus and two 8 bit output buses for result and an output for carry.

2.5.4. oc8051_pc

Module oc8051_pc is actually a program counter. It computes the value of address for next instruction.

Input in module is operation code with which we compute the value for address. There are also inputs that are used in case of jumps (op2 and op3 in case of absolute jumps, alu input for relative addressing), there are also signals for choosing the source for new pc (pc_wr_sel) and a signal which is used if we input new address (wr).

The only output from module is 16 bit current value of program counter.

2.5.5. oc8051_rom

This module contains Program Memory. It depends on the technology we are using for implement oc8051.

Input in module is 16 bit address. Outputs are three 8 bit data buses and ea_int signal. Input address is from first byte of data (data1), second and third byte (data2, data3) are on the following addresses. This is needed for uninterrupted functioning of pipeline.

Ea_int signal is equal to external ea signal, it is activated if the used address is to big for internal Program Memory and we need to access external Program Memory.

2.5.6. oc8051_comp

Function of module oc8051_comp is to compare two inputs and set output if the inputs are the same. Module is needed for computing conditions at conditional jumps. There are different options for comparing the inputs: - ACC vs. zero

- result of arithmetic operation vs. zero - carry

- bit carry (from memory)

These options are enough for all conditional jumps in 8051. Output is connected to oc8051_decoder input, where is transferred to pc_wr when needed.

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2.5.7. oc8051_op_select

All data coming from Program Memory goes through this module. It has three assignments. First assignment is to choose which memory will be used, internal or external. In this assignment the module is functioning like a multiplekser: it has ea and ea_int signals for inputs (if anyone of this two signals is low there is a read cycle from external memory) and an output. Second assignment for this module is interrupt intake. For this purpose this module, beside three 8 bit inputs, has also two input signals for receiving interrupts. These are signal int and 8 bit int_v. We have an interrupt if int signal is set and on the 8 bit bus we receive address of interrupt program (upper 8 bits are zeros). At interrupt we check if the instruction currently executing is 'longer' then one clock cycle (input signal rd) and then LCALL operation code is sent to first output. On other two outputs address of interrupt program is sent. Last assignment of this module is checking operation code and sending memory address, for writing the result, to the output. This is used with instructions that need DPTR for computing results and with instructions that use B register. With this option for immediate addressing mode later on is achieved. We have to be careful, because with this we have two different outputs for second operand, one for immediate operand in ALU and the other for direct addressing.

2.5.8. oc8051_regX

Oc8051_regX modules represent X bit registers, which only function is to delay signal for one clock cycle. Besides input for clock and reset they also have data input and output.

2.6. Data Memory and SFRs

In this section the modules which can contain data will be described. They share same address space, so they all have some common input signals. These signals are: - clk clock

- rst reset. Reset values are written oc8051_defines.v file. - wr writing - wr_addr address to where data is written - data_in input data - wr_bit defines if the instruction is bit addressable - bit_in bit input (for use only with bit addressable instructions and Data Memory)

SFRs has to be checked every clock period if this is a write cycle (wr signal), if it is bit addressable and if the address matches the data will be written to the register. We also have to allow that the address for bit or byte addressable instructions differs. Physical addresses are defined in oc8051_defines.v file.

Beside already mentioned inputs memory also have input for data address and data output. All SFRs also have output from where current value of register can be read and a few special outputs that will be described in the following section. www.opencores.org

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2.6.1. oc8051_ram_top

This module contains Data Memory. It works like some sort of intermediate between ordinary memory and the kind of memory we need (capable of bit addressing). In the bit addressing mode we have to use right bit from the address byte. When ther is a write cycle the whole byte has to be read, appropriate bit changed and all byte has to be written back to the memory. Submodule of this module is oc8051_ram. This module depends on technology we use and it is an ordinary memory with 8 bit address. Simultaneus reading and writing is demanded because of the pipeline.

2.6.2. oc8051_acc

The most used SFR is Accumulator (ACC). Besides standard ports it also has 8 bit input for second ALU result (data2_in) and signal wad2 which activates writing of second result to register. There is another output for parity (p).

2.6.3. oc8051_b_register

B register is simple bit addressable register without special features.

2.6.4. oc8051_psw

This module contains Program Status Word (PSW) register (figure 7). Beside standard inputs it also has input signal p (parity) from accumulator, auxiliary carry and overflow from ALU and signal set that defines what should be written to register. cyacf0rs1rs0ov-p Figure 7 Program status word (PSW)

Cy

Ac f0 rs1 rs0 Ov - P

psw.7 psw.6 psw.5 psw.4 psw.3 psw.2 psw.1 psw.0

carry

auxiliary carry flag 0

register bank selector 1 register bank selector 0 overflow

user definable parity

2.6.5. oc8051_dptr

This module contains 16 bit Data Pointer. It has two 8 bit outputs (data_hi and data_lo) and 8 bit input bus for second ALU result and 2 bit signal that is used when we use instructions that treat DPTR as 16 bit register.

This register is not bit addressable.

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2.6.6. oc8051_sp

This module represents Stack Pointer. Besides stndard inputs it also has two input signals connected to oc8051_decoder. This two signals define from where read or write address will be taken.

2.6.7. oc8051_ports

This module takes care of input-output ports. It has four 8 bit input buses and four 8 bit output buses. This signals are used for communicating with environment. Input to module is also 8 bit current address. This module also has rmw signal, which tells us if the instruction is so called read-modify-write instruction. With these instructions we don't read input pins of module but registers of output ports. These instructions are: - ANL - ORL - XRL - JBC - CPL - INC - DEC - DJNZ

- MOV PX.Y, C - CLR PX.Y - SETB PX.Y

2.6.8. oc8051_tc

This module contains the description of oc8051 timers. There are two timers: Timer/Counter 0 (T/C 0) and Timer/Counter 1 (T/C 1). Both timers are 16 bit long and are represented by two 8 bit registers each (TL0 and TH0 for T/C 0, TL1 and TH1 for T/C 1). This module also contains SFR TMOD, which defines timer modes. You can see detailes on figure 8. gatec/tm1m0gatec/tm1m0 Figure 8 Timer mode register (TMOD) timer 1 bits 7-4, timer 0 bits 3-0

gate sofrtware/hardware run control c/t counter / timer m1 mode selector 1 m0 mode selector 0

Four input signals ie0, ie1, tr0, tr1 represent conditions that activate timers. There are also two output signals tf0 and tf1, those signals set overflow flags in TCON register and 8 bit output bus (data_out) from which we can read current value of the chosen register (TMOD, TL0, TH0, TL1, TH1).

Timers can operate in four different modes:

mode 0: both timers are 8-bit counters with divide-by-32 prescaler, that gives us a 13-bit counter. Only lower five bits of TLx register are used. www.opencores.org

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mode 1: both registers are 16-bit counters

mode 2: THx represents 8-bit counter which is filled with TLx content at overflow

mode 3: in this mode t/c1 just holds constant value. While t/c0 is used as two separate 8-bit counters. TH0 uses control signals from timer0 (TR0 in TF0), while TL0 is using control signals from timer1 (TR1 in TF1).

2.6.9. oc8051_int

This is interrupt module. It accepts interrupt requests and under defined conditions dispatches these requests to the processor. In oc8051 core we have five different interupt sources and each has special address for its service rutine. These addresses are:

- external interrupt 0 (0003H) - timer 0 overflow (000BH) - external interrupt 1 (0013H) - timer 1 overflow (001BH) - serial port interrupt (0023H) This module contains three SFRs:

- timer control register (TCON), contains interrupt flags (figure 9) tf1tr1tf0tr0ie1it1ie0it0 Figure 9 Timer control register (TCON) tf1 tr1 tf0 tr0 ie1 it1 ie0 it0

tcon.7 tcon.6 tcon.5 tcon.4 tcon.3 tcon.2 tcon.1 tcon.0

timer 1 overflow timer 1 run

timer 0 overflow timer 0 run

external interrupt 1 interrupt 1 control bit external interrupt 0 interrupt 0 control bit

- interrupt enable (IE), enables or disables ea--eset1ex1et0ex0 Figure 10 Interrupt enable register (IE) Ea - - Es et1 ex1 et0 ex0

ie.7 ie.6 ie.5 ie.4 ie.3 ie.2 ie.1 ie.0

global enable / disable not used not used

serial port interrupt enable / disable

timer 1 overflow interrupt enable / disable external interrupt 1 enable / disable

timer 0 overflow interrupt enable / disable external interrupt 0 enable / disable

- interrupt priority (IP), in this register priority of specific interrupts is set. oc8051 uses two priority levels. When appropriate bit is set the priority of its interrupt source is increased. www.opencores.org

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Figure 11 Interrupt priority register (IP) - - - Ps pt1 px1 pt0 px0

ip.7 ip.6 ip.5 ip.4 ip.3 ip.2 ip.1 ip.0

not used not used not used

serial port interrupt priority

timer 1 overflow interrupt priority external interrupt 1 priority

timer 0 overflow interrupt priority external interrupt 0 priority

Module has five interrupt inputs, each for every interrupt source. There are two more input signals, signal reti which is set when interrupt ends and signal ack which is set high when processor vectors to interrupt rutine. Module also has 8 bit bus that is used for fetching interrupt vector address.

2.6.10. oc8051_uart

This module contains oc8051 serial interface (uart). Besides standard inputs it also has an input for receive signal (rxd) and an input for transmit signal (txd). These two signals are also outputs from the processor. There is also a timer1 overflow input and an output for interrupts. Modul contains three SFRs: serial control (scon), serial data buffer (sbuf) and power control (pcon).

With scon all operations of uart are controlled (figure 12). sm0sm1sm2rentb8rb8tiri Figure 12 Serial control register (SCON) sm0 sm1 sm2 ren tb8 tr8 ti ri

scon.7 scon.6 scon.5 scon.4 scon.3 scon.2 scon.1 scon.0

serial port mode 0 serial port mode 1

enables multiprocessor feature enable / disable reception 9 bit to transmit 9 bit received transmit interrupt receive interrupt

Serial interface has four operational modes:

mode 0: 8 data bits are transfered. Baud rate is 1/12 of oscillator frequency.

mode 1: 10 bits are transfered (8 data bits and start and stop bit). Baud rate is variable.

mode 2: 11 bits are transfered: start bit, 8 data bits, programable ninth bit and stop bit. Baud rate is 1/32 if smod is set or 1/64 of oscillator frequency otherwise.

mode 3: 11 bits are transfered: start bit, 8 data bits, programable ninth bit and stop bit. Baud rate is variable.

When in mode 1 or 3 timer1 is needed for computing the baud rate (baud rate = (2^smod/64)*(timer 1 overflow rate)).

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2.6.11. oc8051_indi_addr

This module does not contain any SFR but it still contains a part of Data Memory. It contains data from R0 and R1 registers from all register banks. This registers are used for indirect addressing. Input in module are two bits with which we choose a specific register bank and last part of operation code for choosing between registers R0 or R1. This is needed so the address of operand at indirect addressing is already available in first clock cycle and there is no need to stop the pipeline.

2.6.12. oc8051_ram_sel

This module represents a multiplekser which on the base of a read address sends correct data to the data bus. We can choose between data from the memory or from any of the specail registers. This ensures that we get right data even when addressing SFRs (direct or indirect addressing).

2.7. Multipleksers

As it was already mentioned bus management is based on multipleksers. This chapter describes multipleksers in oc8051 design and their functions. Their main feature is that they choose (based on the signal from oc8051_decoder module) one of the inputs (mainly 8 bits wide) and transfer it to output.

2.7.1. oc8051_alu_src1_sel

This module is used to choose first ALU operand. There are immediate operand, accumulator, data from intrernal memory or data from external memory available.

2.7.2. oc8051_alu_src2_sel

This module is used to choose second ALU operand. There are immediate operand, accumulator, data from both memories (internal, external) or zero available.

2.7.3. oc8051_alu_src3_sel

This module is used to choose third ALU operand: from program counter or from DPTR.

2.7.4. oc8051_cy_select

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With this module we choose which carry will be sent to ALU: from PSW, bit data from memory, zero or one.

2.7.5. oc8051_ext_addr_sel

Used for choosing address for external memory: R0 or R1 (same as indirect addressing) or DPTR.

2.7.6. oc8051_immediate_sel

Selection of immediate operand. There are two outputs, for first and second ALU operand. We can choose between PC, second or third instruction byte.

2.7.7. oc8051_ram_rd_sel

Selection of read address: register (R0-R7), indirect address, stack or direct address. When we address registers there are only five bits used (upper three are always zero).

2.7.8. oc8051_ram_wr_sel

Selection of write address: register (R0-R7), indirect address, stack, direct address, accumulator, DPTR or B register.

2.7.9. oc8051_rom_addr_sel

Selection of Program Memory address: PC or DPTR (only at MOVC instruction).

2.8. Instruction execution

For complete overview we have to take a look over three clock cycles.

First clock cycle: Instruction is not fetched yet. Based on previous value of PC and operation code new PC value is computed. This gives as the address of the next instruction. In the next step new op code and operands are fetched from Program Memory.

Second clock cycle: This is first execution cycle. In this period operation code is forwarded to oc8051_pc module, where new PC is computed and to oc8051_decoder module, where all control signals are set. All signals, except internal Data Memory read address signal are delayed for one clock cycle (with oc8051_regX modules). With this delay we achieve that at next active front operand is read from internal Data Memory, control signals and other possible immediate operands are saved to registers.

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Third clock cycle: This is second, last execution cycle. I this cycle signals reach their destination. With oc8051_alu_src1 and oc8051_alu_src2 ALU operand are chosen. Operation in ALU is executed and result(s) is written to selected address in memory.

oc8051_alu_src1_selsrc1immediate1_roc8051_alu_src2_selimmediate2_rsrc2src_sel1_rimediatedataacc, ram_outsrc_sel2_rRsrc_sel1Rsrc_sel2oc8051_ram_rd_selram_rd_selrd_addroc8051_alualu_op_rRalu_opoc8051_decoderaddresssourcesoc8051_ram_wr_selwr_addrRwr_addr_rRAM and SFRram_wr_seldes1 Figure 13 Instruction execution

Most instructions are done like described above. Exceptions are program jumps and instruction for Program Memory read (MOVC).

In next chapters we will go through instruction groups and their specific features.

2.8.1. Arithmetic and logic instructions

Main characteristic of these instructions is that we have to define both ALU operands and ALE operation. Exceptions among these instructions are MUL (multiply) instruction Div (divide) instruction. Difference between these two and the other instructions is in result. When MUL or Div are executed we get 16 bit result and half of it is saved to B register (result1), second half (result2) is saved to ACC. This is achieved if the result is normally written to B register, then wad2 signal is set and with this second result is written to ACC.

Another exception is also INC DPTR instruction, which addresses 16 bit DPTR register. Desired effect is achieved with ALE source3, where upper 8 bits are forwarded, zeros are forwarded to source2, input carry is set to 1, and then add operation is executed. Next instructions are included in this group: - ADD add

- ADDC add with carry - SUBB subtract with carry - INC increase by 1 - DEC decrease by 1 - MUL multiply www.opencores.org

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divide

decimal adjust logical and logical or logical xor clear

rotation left

rotation left with carry rotation right

rotation right with carry swap bits

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2.8.2. Data transfer instructions

This group contains instructions that do not change data value, they just transfer the data to another memory location. ALU operation is fixed to oc8051_alu_nop, which only transfers data from input to output from where it is written to desired location. Exceptions are switdh instructions (XCH and XCHD) where ALE operation oc8051_alu_xch is used.

This instruction group also contains instructions for external memory handling. Picture belows shows a detail from kernel that manages external Data Memory. Read address is chosed with oc8051_ext_addr_sel multiplekser, input data is available in the next clock cycle. Data is available like an option on the multiplekser with which we choose ALE source 1. With the normal procedure data is then written to the internal memory. When writting we only need address and write_x signal and there should be signal from ACC on the output pins.

16 bit wide address8 bit wihe data inputoc8051_alu_src1_seloc8051_accoc8051_ext_addr_selsrc18 bit wide data outputdptr_hidptr_lorioc8051_dptrext_addr_selwrite_poc8051_indi_addroc8051_decoderRwritewrite signal,active high

Figure 14 External rom access

Special instruction for data transfer is also instruction for data transfer from Program Memory. With this instruction we use another multiplekser (oc8051_rom_addr_sel) for address chosing, this multiplekser does not send PC value to output this time but instead it sends ALU operation result. Data is recieved in the next clock cycle as an immediate operand. This instruction takes two clock cycles.

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2.8.3. Bit addressable instructions

These instructions do their operations on bits. They operate same as arithmetic-logical instructions, difference is that instead of ALU source they have bit input and ALU carry, result is available on ALU output. When bit instructions are used we have to take special care when chosing ALU operation. Carry input in ALU is chosen with oc8051_cy_select multiplekser, we can choose between PSW (PSW.7), bit output from memory, logical 1 or logical 0. First two options are used in operations, second two are used for setting (or reseting) particular bits.

bti_outoc8051_cy_selectalu_cybit_outpsw[7]cy_sel_rRcy_seloc8051_alualu_op_rRalu_opoc8051_decoderRAM and SFRdesCy Figure 15 Bit addressable instruction

This group also contains jump instructions (JC, JNC, JB, JNB and JBC) Which will be decribed more thoroughly in next section. Other instructions in this group are: - ANL - ORL - MOV - CLR - SETB - CPL

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2.8.4. Program jumps

Program jumps are not very similar to other instructions in their execution. The fact that they change PC value is enough that we have to stop the pipeline and wait to get first instruction from new address.

Considering the time we spend on each instruction program jumps can be diveded to three groups:

First group contains instructions that need two clock cycles. These instructions have the value for new PC represented as immediate operand (ACALL, AJMP, LCALL in LJMP). With these instructions new value is written to PC and we simply wait for new instruction.

Second group of instructions needs three clock cycles to execute. These jumps get new address (new PC value) as a sum from current PC (or DPTR in case of JMP ☺) and immediate operand which is represented as tows-complement. Instructions in this group are: - JC - JNC - JB - JNB - JBC - SJMP - JMP - JZ - JNZ

Third and last group contains instructions that need four clock cycles to finish their job. These instructions are:

- CJNE, is similar to instruction from prior group, but needs another clock cycle for setting carry flag - RET - RETI

2.8.5. Addressing modes

We already get to know some addressing modes, when we described 8051 microcontroller. In this chapter we will concetrate on addressing modes within oc8051.

There are two modules that control addressin modes, oc8051_ram_rd_sel and oc8051_ram_wr_sel.

Those two modules are multipleksers with which we choose from which address we will read and to which we will write. Operands that do not need a read from memory (immediate operands) are selected with oc8051_immediate_sel multiplekser. The last word at selecting the data source has another pair of multipleksers oc8051_alu_src1_sel and oc8051_alu_src1_sel. With them we can choose between data from the Data Memory, from the ACC or immediate operand. The different addressing modes are:

- direct addressing: We choose direct address with multipleksers (read OC8051_RRS_D – operand 2, write OC8051_RWS_D operand 2 and OC8051_RWS_D3 operand 3) and data from the Program Memory is sent to the bus. - indirect addressing: For indirect addressin registers R0 and R1 from the chosen register bank are used, module oc8051_indi_addr is used for this, module saves registers that could be useful and then considering which register bank is chosen and www.opencores.org

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-

-

-

-

last bit of operation code selects the register we might need. Multipleksers for address selecting (oc8051_RRS_I and oc8051_RWS_I) must be set to indirect addressing. Stack management also falls into this group of instructions. With modules oc8051_RRS_SP and oc8051_RWS_SP we get stack pointer value on addressing bus, module oc8051_sp is used for increasing or decreasing the pointer value.

register inctructions: When we use register instructions the address has to be selected with OC8051_RRS_RN and OC8051_RWS_RN multipleksers. Final physical address is combined from the last three bits of operation code and two bits for selecting register bank. Upper three bits are always zero.

register-specific instruction: These instructions are mainly specific to Accumulator. ACC read is chosen ALU source select multiplekser. Writing to ACC is chosen with oc8051_ram_wr_sel multiplekser Which offers ACC write as one of the options (OC8051_RWS_ACC). There are also some instructions that are specific to B register or DPTR. This instructions are intercepted in oc8051_op_select modul, needed address is put to second result bus and is treated as direct addressing.

immediate constants: In this address mode the value of a constant follows the opcode. Because of restriction that three bytes are always delivered from memory they are also immediatly available. We choose which one we want to use with oc8051_immediate_sel multiplekser and later on with selecting immediate operand for ALU source. This group also includes Program Counter, so it can also be used for calling subroutines and relative addressing.

indexed addressing: This addressing mode is used solely when addressing Program Memory. At this mode oc8051_rom_addr_sel multiplekser is used. Instead of PC, ALE result is send when next address is computed. Data is received as immediate operand in next clock cycle.

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oc8051_alu_src2_selimmediate2_rsrc1src_sel1_rRsrc_sel2_rimmediate1Rimmediate2acc, ram_outRoc8051_immediate_selRram_rd_seloc8051_ram_rd_selrd_addrspop1_n,{psw[4:3], op1_n[2:0]}op2_n,op3_noc8051_indi_addrripc_hi_r,pc[7:0]oc8051_ram_wr_selwr_addrRRAM and SFRsrc_sel2oc8051_spsrc_sel1oc8051_decoderwr_addr_rram_wr_seloc8051_pcoc8051_op_selectop2_dr Figure 16 Addressing internal ram

2.9. Interrupts

As we had already seen module oc8051_int manages interrupt handling. This module intercepts interrupt, defines address of interrupt program and sends interrupt demand to next module. If interrupt is enabled and none with higher (or same) priority is already processing then modul sets int signal and writes interrupt program address to int_v bus. This interrupt demand is send to oc8051_op_select module which stops execution of current program and starts executing LCALL instruction. When interrupt program finishes (with RETI instruction) oc8051_decoder sets reti signal and communicate oc8051_int module that processing of interrupt is finished so program can be interrupted on this priority level. oc8051_decoderretiint0int1introc8051_op_selectint_srcackoc8051_inttf0tf1int_uartoc8051_tcoc8051_uartprogram rom Figure 17 Interrupts

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3

Verification

This chapter describes a method of testing oc8051 and all on-chip perifery.

The basic idea is that we download the verification program to internal Program Memory and then monitor output of p0, p1 and p2 ports. Port p3 serves for additional testing of perifery.

3.1. Additional modules

3.1.1. oc8051_tb

This is the top module, test bench. It contains connections between oc8051 core and the rest of the verification modules. In this module ports from 0 to 2 are monitored and the data is then compered with the expected data.

3.1.2. oc8051_xram

This module contains external Data Memory. It is important for testing movx instructions.

3.1.3. oc8051_uart_test

This module is used for testing serial interface (uart). It contains modul oc8051_uart whish is the same as in oc8051 core. Using this module communication across serial interface is tested.

3.2. Features

Basic idea is that we run a program on our oc8051 core and monitor output ports. So all test programs must put an unexpected value (error number for example) on output if an error occurs.

Expected values of outputs are saved in oc8051_test.vec file. This file is loaded to buffer in oc8051_tb module and at every change on ports the output vector is compared to the one in the file. When vector XXXX is reached the test is succesfuly finished.

3.3. Port p3

As it was already mentioned port p3 is used for testing the oerifery of the processor. This is the reason that most pins has special assignment: 7 selects between external memory and uart

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1 - external memory 0 - uart

connected to input t1 connected to input t0 connected to input int1 connected to input int0 unused

connected to ow, input to external uart connected to wr_bit, input to external uart

oc8051address, data andcontrol signalsoc8051_xrammuxoc8051_uart_testtxdrxdp3_out.7p3_out.6p3_out.5p3_out.4p3_out.3p3_out.2p3_out.1p3_out.0int0int1t0t1not usedrxdtxdowwr_bit Figure 18 Verification

3.4. Programs

Most programs that we use for testing the core was found on homepage of a similar project (http://www.cs.ucr.edu/~dalton/i8051/).

This programs test only processor, so for testing the perifery a few programs are added: - div16u: additional testing of mul and div instructions - xram_m: testing of external Data Memory - timer_test: timer testing

- counter_test : counter testing - interrupt_test : interrupts testing - serial_test : serial interface testing

- r_bank: testing of psw fourth and fifth bit (register bank choosing)

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