基于51单片机的电子数字钟设计的外文翻译

基于51单片机的电子数字钟设计的外文翻译

AT89C51 Family Users Guide 1 Features

Compatible with MCS-51 Products

4K Bytes of In-System Reprogrammable Flash Memory – Endurance 1000 WriteErase Cycles Fully Static Operation 0 Hz to 24 MHz Three-level Program Memory Lock 128 x 8-bit Internal RAM 32 Programmable IO Lines Two 16-bit TimerCounters Six Interrupt Sources

Programmable Serial Channel

Low-power Idle and Power-down Modes 2 Description

The AT89C51 is a low-power high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory PEROM The device is manufactured using Atmels high-density nonvolatile memory technology

and is

compatible

with

the industry-standard

MCS-51

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instruction set and pin-out The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer By combining a versatile

8-bit CPU with Flash on a monolithic

chip the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications

3 Pin Configurations

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4 Lock Diagram

The AT89C51 provides the following standard features 4K bytes of Flash 128 bytes of RAM 32 IO lines two 16-bit timercounters a five vector two-level

interrupt

architecture

a full

duplex serial

port on-chip

oscillator and clock circuitry In addition the AT89C51 is designed with static

logic

for operation

down to zero frequency and supports two

software selectable power saving modes The Idle Mode stops the CPU while allowing

the RAM timercounters

serial

port and interrupt

system to

continue functioning The Power-down Mode saves the RAM contents but freezes the oscillator hardware reset

5 Pin Description VCC Supply voltage GND Ground Port 0

Port 0 is an 8-bit open-drain bi-directional

IO port As an output port

disabling all other chip functions until the next

each pin can sink eight TTL inputs When 1s are written to port 0 pins the pins can be used as high-impedance inputs

Port 0 may also be configured

to be the multiplexed

low-order

addressdata bus during accesses to external program and data memory In this mode P0 has internal pull-ups

Port 0 also receives the code bytes during Flash programming and

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outputs the code bytes during program verification required during program verification

Port 1

Port 1 is an 8-bit bi-directional Port 1 output buffers

External pull-ups are

IO port with internal pull-ups The

can sinksource four TTL inputs When 1s are written

to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs As inputs Port 1 pins that are externally

being pulled low

will source current IIL because of the internal pull-ups Port 1 also receives verification

Port 2

Port 2 is an 8-bit bi-directional Port 2 output buffers

IO port with internal

pull-ups The

the low-order

address bytes during Flash programming and

can sinksource four TTL inputs When 1s are written

to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs As inputs Port 2 pins that are externally

being pulled low

will source current IIL because of the internal pull-ups Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses MOVX DPTR In this application it uses strong internal pull-ups when emitting 1s During accesses to external data memory that uses 8-bit addresses MOVX RI Port

2 emits the contents of the P2 Special Function

Register Port 2 also receives the high-order address bits and some control

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signals during Flash programming and verification

Port 3

Port 3 is an 8-bit bi-directional Port 3 output buffers

IO port with internal

pull-ups The

can sinksource four TTL inputs When 1s are written

to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs As inputs Port 3 pins that are externally will source current IIL because

being pulled low

of the pull-ups Port 3 also serves the

functions of various special features of the AT89C51 as listed below

Port Pin

Alternate Functions

P30 RXD serial input port P32 INT0 external interrupt 0

P34 T0 timer 0 external input P36 WR external data memory write

Port

3

P31 TXD serial output port P33 INT1 external interrupt 1 P35 T1 timer 1 external input strobe

P37 RD external data memory read strobe

also receives some control signals for Flash programming and verification

RST

Reset input A high on this pin for two machine cycles while the oscillator is running resets the device

ALE

Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory This pin is also the program pulse input PROG during Flash programming In normal operation ALE is emitted at a constant rate of 16 the oscillator

frequency and may be used

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for external timing or clocking purposes Note however that one ALE pulse is skipped during each access to external Data Memory If desired ALE operation can be disabled by setting bit 0 of SFR location 8EH With the bit set ALE is active only during a MOVX or MOVC instruction Otherwise the pin is weakly pulled high Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode

Program Store Enable is the read strobe to external program memory When the AT89C51 is executing code from external program memory is activated twice each machine cycle except that two activations are skipped during each access to external data memory

VPP

External Access Enable must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH Note however that if lock bit 1 is programmed will be internally latched on reset should be strapped to VC C for internal

program executions This pin also receives the 12-volt programming enable voltage VPP during

XTAL1

Input to the inverting clock operating circuit

XTAL2

oscillator

amplifier

and input to the internal

Flash programming for parts that require 12-volt VPP

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Output from the inverting oscillator amplifier 6 Oscillator Characteristics

XTAL1 and XTAL2 are the input and output respectively amplifier

of an inverting

as shown

which can be configured for use as an on-chip oscillator

in Figure 1 Either a quartz crystal or ceramic resonator may be used To drive the device from an external clock source XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2 There are no

requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a divide-by-two flip-flop but minimum and imum voltage high and low time specifications must be observed

Oscillator Connections

Note C1 C2 30 pF±10 pF for Crystals40 pF±10 pF for Ceramic ResonatorsExternal Clock Drive Configuration 7 Idle Mode

In idle mode the CPU puts itself to sleep while all the on-chip peripherals

remain active The mode is invoked by software The content of

remain unchanged

the on-chip RAM and all the special functions registers

during this mode The idle mode can be terminated by any enabled interrupt or by a hardware reset It should be noted that when idle is terminated by a hard ware reset the device normally resumes program execution from

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where it left off up to two machine cycles before the internal reset algorithm takes control On-chip hardware inhibits

access to internal

RAM

in this event but access to the port pins is not inhibited To eliminate the possibility

of an unexpected write

to a port pin when Idle is

terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory

8 Power-down Mode

In the power-down mode the oscillator

is stopped and the instruction

executed The on-chip RAM

that invokes power-down is the last instruction

and Special Function Registers retain their values until the power-down

mode is terminated The only exit from power-down is a hardware reset Reset redefines the SFRs but does not change the on-chip RAM The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize

9 Programming the Flash

The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state that is contents FFH and ready to be programmed The programming interface accepts either a high-voltage 12-volt or a low-voltage VCC program

enable signal The low-voltage programming mode

provides a convenient way to program the AT89C51 inside the users system while the high-voltage programming mode is compatible with conventional

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third party Flash or EPROM programmers The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled The respective top-side marking and device signature codes are listed in the following table

The AT89C51 code memory array is programmed byte-by-byte in either programming mode To program any nonblank byte in the on-chip Flash Memory the entire memory must be erased using the Chip Erase Mode

10 Flash Programming and Verification Characteristics TA 0°C to 70°C VCC 50±10

Note 1 Only used in 12-volt programming mode 11 DC Characteristics

TA -40°C to 85°C VCC 50V±20 unless otherwise noted Notes

1 under steady state externally limited as follows

imum IOL per port pin 10 mA imum IOL per 8-bit port Port 0 26 mA Ports 1 2 3 15 mA

imum total IOL for all output pins 71 mA If IOL exceeds the test

condition

VOL may exceed the related

non-transient

conditions

IOL must be

specification Pins are not guaranteed to sink current greater than the listed test conditions

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