Hot-Socketing Specifications
4.Hot Socketing &Power-OnReset
Stratix® II devices offer hot socketing, which is also known as hot plug-in or hot swap, and power sequencing support without the use of any external devices. You can insert or remove a StratixII board in a system during system operation without causing undesirable effects to the running system bus or the board that was inserted into the system. The hot socketing feature also removes some of the difficulty when you use Stratix II devices on printed circuit boards (PCBs) that also contain a mixture of 5.0-, 3.3-, 2.5-, 1.8-, 1.5- and 1.2-V devices. With the StratixII hot socketing feature, you no longer need to ensure a proper power-up sequence for each device on the board.The StratixII hot socketing feature provides:
■Board or device insertion and removal without external components or board manipulation
■Support for any power-up sequence
■
Non-intrusive I/O buffers to system buses during hot insertion
This chapter also discusses the power-on reset (POR) circuitry in StratixII devices. The POR circuitry keeps the devices in the reset state until the VCC is within operating range.
Stratix II devices offer hot socketing capability with all three features listed above without any external components or special design requirements. The hot socketing feature in Stratix II devices allows:
■The device can be driven before power-up without any damage tothe device itself.
■
I/O pins remain tri-stated during power-up. The device does notdrive out before or during power-up, thereby affecting other buses in operation.
■
Signal pins do not drive the VCCIO, VCCPD, or VCCINT power supplies. External input signals to I/O pins of the device do not internallypower the VCCIO or VCCINT power supplies of the device via internalpaths within the device.
Timing Model
Table5–34.Output Timing Measurement Methodology for Output Pins
Loading and Termination
RS (Ω)
LVTTL (4)LVCMOS (4)2.5 V (4)1.8 V (4)1.5 V (4)PCI (5)PCI-X (5)SSTL-2 Class ISSTL-2 Class IISSTL-18 Class ISSTL-18 Class II1.8-V HSTL Class I1.8-V HSTL Class II1.5-V HSTL Class I1.5-V HSTL Class II1.2-V HSTL with OCTDifferential SSTL-2 Class IDifferential SSTL-2 Class IIDifferential SSTL-18 Class IDifferential SSTL-18 Class II1.5-V Differential HSTL Class I1.5-V Differential HSTL Class II1.8-V Differential HSTL Class I1.8-V Differential HSTL Class IILVDS
HyperTransportLVPECL
Notes to Table5–34:(1)(2)(3)(4)(5)
Notes(1), (2), (3)
Measurement
Point
VTT (V)
CL (pF)
000001010
1.1231.1230.7900.7900.7900.7900.6480.6481.1231.1230.7900.7900.6480.6480.7900.790
00000000000000000000
I/O Standard
RD (Ω)RT (Ω)VCCIO (V)
3.1353.1352.3751.7101.4252.9702.970
VMEAS (V)
1.56751.56751.18750.8550.71251.4851.4851.16251.16250.830.830.830.830.68750.68750.5701.16251.16250.830.830.68750.68750.830.831.16251.16251.5675
252525255025505050255025505025
100100100
50255025502550255025502550255025
2.3252.3251.6601.6601.6601.6601.3751.3751.1402.3252.3251.6601.6601.3751.3751.6601.6602.3252.3253.135
Input measurement point at internal node is 0.5 × VCCINT.
Output measuring point for VMEAS at buffer output is 0.5 × VCCIO.
Input stimulus edge rate is 0 to VCC in 0.2 ns (internal signal) from the driver preceding the I/O buffer.Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV rippleVCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table5–41.M4K Block Internal Timing Microparameters(Part 2 of2)
-3 SpeedGrade (2)Min (4)
22203222032220322203334
Note(1)-4 SpeedGradeMin (5)
Max
-5 SpeedGradeMin (4)
Max
ps ps ps ps ps ps ps ps 701
ps
SymbolParameter
-3 Speed
Grade (3)Min (4)
Max
Unit
Max
tM4KDATAASUtM4KDATAAH tM4KADDRASUtM4KADDRAH tM4KDATABSUtM4KDATABH
A port data setup time before clock
A port data hold time after clock
A port address setup time before clockA port address hold time after clock
B port data setup time before clock
B port data hold time after clock
23 213 23 213 23 213 23 213524
334
2525 233233 2525 233233 2525 233233 2525 233233549
3193341,5401,6161,4371,4371,4371,437 165165
29 272 29 272 29 272 29 272601
334
tM4KRADDRBSUB port address setup
time before clocktM4KRADDRBHtM4KDATACO1
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
tM4KDATACO2(6)tM4KCLKHtM4KCLKL tM4KCLR
1,6162,453 1,6161,3121,312 1512,5742,820 1,6163,286 ps 1,675 1,675 192ps ps ps Minimum clock high time1,250Minimum clock low timeMinimum clear pulse width
1,250144
Notes to Table5–41:(1)(2)(3)(4)(5)(6)
FMAX of M4K Block obtained using the QuartusII software does not necessarily equal to 1/TM4KRC.These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade devices offer the industrial temperature grade.
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second number is the minimum timing parameter for commercial devices.
Numbers apply to unpacked memory modes, true dual-port memory modes, and simple dual-port memory modes that use locally routed or non-identical sources for the A and B port registers.
Stratix II Device Handbook, Volume 1
Document Revision History
Stratix II Device Handbook, Volume 1
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