Circuit arrangement for adding or subtracting oper

专利名称：Circuit arrangement for adding or

subtracting operands coded in BCD-code orbinary-code

发明人：Horst Fischer,Wolfgang Rohsaint申请号：US07/613889申请日：19901207公开号：US05146423A公开日：19920908

摘要：It is possible to add or subtract operands coded in binary coded decimal (BCD)code or in the binary code with the circuit arrangement upon employment of a singlebinary adder. In order to enable BCD operations, the BCD operations are supplied to thebinary adder (DA) via input stages (EG1, EG2). The one input stage (EG1) inverts theallocated operand (A) when this operand has a minus sign. The other input stage (EG2)edits the allocated operand (B) such that, given positive operands, (A, B), the number 6 isadded to the allocated operand (B) and the result is inverted given negative operands (A,B). Given operands in the binary code, the allocated operands are inverted when they areprovided with a minus sign; otherwise, they are not influenced. After the operation of theedited operands (X, Y) in the binary adder (DA), a correction of the sum result (S) can berequired given BCD operation. This is the case when a carry signal (C) in the binaryoperation in the binary adder (DA) has appeared at the most significant place of the sumresult. In this case the number 6 is subtracted from the sum result (S) in an output stage(AGS). This leads to the corrected sum (R). Upon employment of a single binary adder, itis possible to add and to subtract BCD numbers and binary numbers with the circuit

arrangement.

申请人：SIEMENS AKTIENGESELLSCHAFT

代理机构：Hill, Van Santen, Steadman & Simpson

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