MT40A512M16JY-083E IT_B

All other commands except those listed in the following sequences are illegal.1.Issue MR4[5] 1 to enter sPPR mode enable.

a.All DQ are driven HIGH.

2.Issue four consecutive guard key commands (shown in the table below) to MR0with each command separated by tMOD. Please note that JEDEC recently addedthe four guard key entry used for hPPR to sPPR entry; early DRAMs may not re-quire four guard key entry code. A prudent controller design should accommodateeither option in case an earlier DRAM is used.

a.Any interruption of the key sequence by other commands, such as ACT, WR,RD, PRE, REF, ZQ, and NOP, are not allowed.

b.If the guard key bits are not entered in the required order or interrupted withother MR commands, sPPR will not be enabled, and the programming cyclewill result in a NOP.

c.When the sPPR entry sequence is interrupted and followed by ACT and WRcommands, these commands will be conducted as normal DRAM com-mands.

d.JEDEC allows A6:0 to be \"Don't Care\" on 4Gb and 8Gb devices from a suppli-er perspective and the user should rely on vendor datasheet.

Table 44: PPR MR0 Guard Key Settings

MR0First guard keySecond guard keyThird guard keyFourth guard keyBG1:00000BA1:00000A17:12xxxxxxxxxxxxxxxxxxxxxxxxA111010A101100A90111A80111A71111A6:011111111111111111111111111113.After tMOD, issue an ACT command with failing BG and BA with the row addressto be repaired.

4.After tRCD, issue a WR command with BG and BA of failing row address.

a.The address must be at valid levels, but the address is a \"Don't Care.\"5.All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7)after WL (WL = CWL + AL + PL) in order for sPPR to initiate repair.

a.Repair will be initiated to the target DRAM only if all DQ during bit 0 throughbit 7 are LOW.

b.Repair will not be initiated to the target DRAM if any DQ during bit 0 throughbit 7 is HIGH.

1.JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If HIGHis driven to all DQs of a DRAM consecutively for equal to or longer thanthe first 2tCK, then DRAM does not conduct hPPR and retains data ifREF command is properly issued; if all DQs are neither LOW for 4tCKnor HIGH for equal to or longer than the first 2tCK, then hPPR mode ex-ecution is unknown.

c.DQS should function normally.

6.REF command may NOT be issued at anytime while in sPPR mode.

7.Issue PRE after tWR time so that the device can repair the target row during tWRtime.

a.Wait tPGM_Exit_s after PRE to allow the device to recognize the repaired tar-get row address.

8Gb: x4, x8, x16 DDR4 SDRAM

sPPR Row Repair

Table 45: DDR4 sPPR Timing Parameters DDR4-1600 through DDR4-3200

ParametersPPR programming timesPPR precharge exit timesPPR exit timeSymboltPGM_stPGM_Exit_stPGMPST_sMint RCD(MIN)+ WL + 4nCKMax–––Unitnsnsns+tWR(MIN)20tMOD8Gb: x4, x8, x16 DDR4 SDRAMhPPR/sPPR Support Identifier

hPPR/sPPR Support Identifier

Table 46: DDR4 Repair Mode Support Identifier

MPR Page 2MPR0A7UI0hPPR1A6UI1sPPR2A5UI2RTT_WRA4UI3A3UI4A2UI5CRCA1UI6RTT_WRA0UI7Temp sensor8Gb: x4, x8, x16 DDR4 SDRAM

PRECHARGE Command

Figure 82: tFAW Timing

CK_cCK_tCommand

T0Ta0Tb0Tc0Tc1Tc2Td0Td1ACTValidtRRDACTValidtRRDACTValidtRRDACTValidValidValidACTNOP tFAWValidValidBankGroup(BG)BankAddress

ValidValidValidValidValidValidValidValidValidValidValidValidValidDon’t CareTime Break

Note:

1.tFAW; four activate windows.

PRECHARGE Command

The PRECHARGE command is used to deactivate the open row in a particular bank orthe open row in all banks. The bank(s) will be available for a subsequent row activationfor a specified time (tRP) after the PRECHARGE command is issued. An exception tothis is the case of concurrent auto precharge, where a READ or WRITE command to adifferent bank is allowed as long as it does not interrupt the data transfer in the currentbank and does not violate any other timing parameters.

After a bank is precharged, it is in the idle state and must be activated prior to any READor WRITE commands being issued to that bank. A PRECHARGE command is allowed ifthere is no open row in that bank (idle state) or if the previously open row is already inthe process of precharging. However, the precharge period will be determined by thelast PRECHARGE command issued to the bank.

The auto precharge feature is engaged when a READ or WRITE command is issued withA10 HIGH. The auto precharge feature uses the RAS lockout circuit to internally delaythe PRECHARGE operation until the ARRAY RESTORE operation has completed. TheRAS lockout circuit feature allows the PRECHARGE operation to be partially or com-pletely hidden during burst READ cycles when the auto precharge feature is engaged.The PRECHARGE operation will not begin until after the last data of the burst write se-quence is properly stored in the memory array.

质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工业级IC，军级二三极管，功率管等;

应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备祝您:工作顺利，生活愉快!

以深圳市美光存储技术有限公司提供的参数为例，以下为MT40A512M16JY-083E IT_B的详细参数，仅供参考

8Gb: x4, x8, x16 DDR4 SDRAM

REFRESH Command

state. A delay between the REFRESH command and the next valid command, exceptDES, must be greater than or equal to the minimum REFRESH cycle time tRFC (MIN),as shown in Figure 83 (page 144).

Note: The tRFC timing parameter depends on memory density.

In general, a REFRESH command needs to be issued to the device regularly every tREFIinterval. To allow for improved efficiency in scheduling and switching between tasks,some flexibility in the absolute refresh interval is provided for postponing and pulling-in the REFRESH command. A limited number REFRESH commands can be postponeddepending on refresh mode: a maximum of 8 REFRESH commands can be postponedwhen the device is in 1X refresh mode; a maximum of 16 REFRESH commands can bepostponed when the device is in 2X refresh mode; and a maximum of 32 REFRESHcommands can be postponed when the device is in 4X refresh mode.

When 8 consecutive REFRESH commands are postponed, the resulting maximum inter-val between the surrounding REFRESH commands is limited to 9 × tREFI (see Figure 84(page 145)). For both the 2X and 4X refresh modes, the maximum interval between sur-rounding REFRESH commands allowed is limited to 17 × tREFI2 and 33 × tREFI4, re-spectively.

A limited number REFRESH commands can be pulled-in as well. A maximum of 8 addi-tional REFRESH commands can be issued in advance or “pulled-in” in 1X refresh mode,a maximum of 16 additional REFRESH commands can be issued when in advance in 2Xrefresh mode, and a maximum of 32 additional REFRESH commands can be issued inadvance when in 4X refresh mode. Each of these REFRESH commands reduces thenumber of regular REFRESH commands required later by one. The resulting maximuminterval between two surrounding REFRESH commands is limited to 9 × tREFI (Fig-ure 85 (page 145)), 17 × tRFEI2, or 33 × tREFI4. At any given time, a maximum of 16 REFcommands can be issued within 2 × tREFI, 32 REF2 commands can be issued within 4 ×tREFI2, and REF4 commands can be issued within 8 × tREFI4 (larger densities arelimited by tRFC1, tRFC2, and tRFC4, respectively, which must still be met).

Figure 83: REFRESH Command Timing

CK_cCK_tCommand

REFDEStRFCT0T1Ta0Ta1Tb0Tb1Tb2Tb3Tc0Tc1Tc2Tc3DESREFDEStRFC (MIN)DESValidValidValidValidValidREFValidValidValidtREFI (MAX 9 × tREFI)DRAM must be idleDRAM must be idleTime BreakDon’t Care

Notes:

1.Only DES commands are allowed after a REFRESH command is registered until tRFC

(MIN) expires.

2.Time interval between two REFRESH commands may be extended to a maximum of 9 ×tREFI.