软件模拟SPI接口

Features

•Upto444KBytes/SecThroughput@10MHz•DirectlySupportsLargeBlockWrites

•EasilyExpandableforMultipleSPISlaves•OperatesinSPIMode0

•16-bitData,EasilyModifiedto8-bitOperation•NoInterruptsRequired

•LowRegisterCount;OnlyThreeNeeded(Twoif8-bitMode)•SmallCodeSize;35Words,IncludingInitialization•

InterfacestoAtmelAT25xxxSerialEEPROM

Introduction

TheSynchronousPeripheralInterface(SPI)standardisgainingrapidlyinpopularity.ItallowsfastercommunicationthanTWIandcanbeimplementedusingfewergateswhichmeanslowersiliconcosts.AlthoughthelargerAVRfamilymembersincludeafullyfunctionalSPIinterface,thesmallermembersdonot.Thisapplicationnotedescribesasetoflow-levelroutinesforsoftwareimplementationoftheSPIprotocol,inMastermode(allcommunicationsoriginatefromtheAVR).ThesecanbeusedasthebasisforcommunicatingwithAtmel’s25XXXfamilyofserialEEPROMmemories,aswellasahostofotherperipheralIC’ssuchasdisplaydrivers.

Figure1.ConnectionBetweentheAVRMCUandtheSlaveDeviceShownasaSerialEEPROM

MASTERSLAVEPB0SCKAVRPB1SSPB2MOSIPB3MISOAT90S1200AT250108-bitMicrocontrollerApplicationNoteRev.1108B–AVR–05/021

Figure2.SPITransmissionTiming

init_spiena_spirw_spi (optional)rw_spidisa_spi(ena_spi)SS16 BITS TOTALSCK16 BITS TOTALMOSI15(MSB)1413210(LSB)MISO15(MSB)1413210(LSB)SAMPLETheoryofOperation

SPIMode0impliesthefollowingconditions:1.TheSCKsignalislowwhenIdle.

2.MOSIdata(fromtheAVR)mustbestableatsometime(setup)beforetherising

edgeoftheclock.3.MISOdata(fromtheSlave)isvalidatsometime(tVALID)afterthefallingedgeof

theclock.4.DataisalwayssentMSBfirst.

Theseroutineshavebeenwrittentomeetthosestandards,withspecialattentionbeingpaidtotheboundaryconditions,suchastVALIDandtSETUP.Thesetimingsaredetailedlaterinthisapplicationnote.Figure3.SPIMasterFlowchart

RESETINITIALIZEinit_spiMAINena_spirw_spiSPI TRANSMISSIONTRANSMIT MORE DATAYESNOdisa_spi2

AVR320

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AVR320

SubroutineDescription

init_spi:

ThisroutineinitializestheSPIportlines.ThemacroswillneedtobemodifiedifPortBisnotused;Otherwise,simplychangingthePortDefinition.EQU’sfortheSCK,MOSI,MISO,andNSS(not-Slave-Select)isadequate.Thisroutinehasnoentryrequirementsandreturnsnothing.ena_spi:

ThisroutinemakessurethatSCKislowbeforesettingSStotheactivestate.Thisroutinehasnoentryrequirementsandreturnsnothing.disa_spi:

ThisroutinebringstheSSsignalhigh(inactive).Itshouldbecalledwhenatrans-missionsequenceiscomplete,topreventspuriousclockingoftheSPISlaves.Italsohasnoentryrequirementsandreturnsnothing.rw_spi:

Thisroutinesends/receiveseitheran8-or16-bitdataword,dependingonwhethertheuserhasmodifiedthesourcecode.ItleavestheSCKsignallowuponexit,anddoesnotmodifytheSSsignal;Therefore,manyback-to-backwritesarepossiblebysimplycallingthisroutinerepeatedly.Entryrequirementsaresimplythatthespi_lo(andspi_hi,ifusedin16-bitmode)areinitializedwiththedatatobesent,priortocallingthisroutine.Uponexit,thesameregister(s)containthedatareceivedfromtheSPISlave.

Conversionto8-bitOperation

Thereareonlytwolinesofcodethatrequiremodificationinorderfortheapplictionnotetoworkwith8-bitdatawords.Bothofthechangesareintherw_spiroutine.First,thebitcounterinitializationvaluemustbechangedfrom16to8;Secondly,theline“rolspi_hi”mustbecommentedout.Nootherchangesarenecessary,exceptthatthespi_hiRegis-terisnolongerneededandisneverused.

Macrosareusedtomakethecodemorereadable.ItisassumedthatPortBwillbeusedfortheSPIinterface;Ifthisisnotthecase,thenthemacrosthemselvesmustbemodi-fiedtoreflectthecorrectport.PinsforthefourSPIsignalsarelistedunder“PORTDEFINITIONS”asEQU’sandareeasilymodified.

Thedelayfunctionmacrosdeservesomeadditionalexplanation.Tohelpconservereg-isters,thisroutinegetsdouble-dutyoutoftheTEMPRegisterbykeepinga5-bitbitcountervalueandthedelaycounterformeasuringtheSCKhighandlowtime.Thelatterarekeptintheuppermostbits.Bysimplyincrementingtheupperthreebitsandwatchingforarollover,wecantracktimewithoutaffectingthelowestfivebits.Notethat,inreality,wearesubtractingvaluesratherthanadding;Theendresultisthesame,exceptthatCarryiscleared(ratherthanset)whenthevalueoftheupperthreebitsrollsfrom7to0.

Macros

3

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Figure4.Setup&HoldTiming

tHILOSCKtSETUPMOSItVALIDMISODelayfromMOSIUpdatetoSCKRisingEdge

ThedelayperiodfromupdatingMOSItotherisingedgeofSCKisacriticalperiod,asitisactuallytheDataSetupTime(tSETUP)fortheconnectedperipheral.Inthisroutine,theamountofsetuptimeistwoclockcyclesifMOSIischangingtolow,threeifchangingtohigh(thisskewallowsfordifferenthi/lodrivelevelsaswell).Ata10MHzclock,thisequatesto200-300ns.Ifmoretimeisrequired,NOPsshouldbeplacedimmediatelybeforethesck_histatement.

SCKwillspendmostofitstimelow,duetothefactthatitislowduringthe“overhead”portionsofthesendloop.However,iftheconnectedperipheralcanhandleafasterrate,theHigh-timeDelay(tHILO)canbereducedtomatchtheminimumSCK-highspecification.

Withadelayvalueofone(1)beingused,theroutinerequiresapproximately22.5AVRclocksperdatabit,andtheSCK-hightimeisexactlyfourclocks.At10MHz,thiswouldcorrespondwithanequivalentSCK-highspecof400ns,andanoverallthroughputof444Kbytes/sec.

Thelow-timedelaymustbesettomeetthe“SCKfalltoMISO(slavedataout)Valid”period(tVALID),whichisdeterminedbytheperipheral.Withadelayvalueofone(1),thisroutinewillhavethreeAVRclocksdelaybeforelatchingtheMISOsignalintothepin’ssynchronizationregister.Again,at10MHz,thisisa300nsperiod,andcanbeadjustedupwardbyincreasingthedelayvalue.

SCKDutyCycle

4

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