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NCP1351

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Variable Off Time PWMController

The NCP1351 is a current−mode controller targeting low poweroff−line flyback Switched Mode Power Supplies (SMPS) where costis of utmost importance. Based on a fixed peak current technique(quasi−fixed TON), the controller decreases its switching frequency asthe load becomes lighter. As a result, a power supply using theNCP1351 naturally offers excellent no−load power consumption,while optimizing the efficiency in other loading conditions. When thefrequency decreases, the peak current is gradually reduced down toapproximately 30% of the maximum peak current to preventtransformer mechanical resonance. The risk of acoustic noise is thusgreatly diminished while keeping good standby power performance.An externally adjustable timer permanently monitors the feedbackactivity and protects the supply in presence of a short−circuit or anoverload. Once the timer elapses, NCP1351 stops switching and stayslatched for version A, and tries to restart for Version B.

The internal structure features an optimized arrangement whichallows one of the lowest available startup current, a fundamentalparameter when designing low standby power supplies.

The negative current sensing technique minimizes the impact of theswitching noise on the controller operation and offers the user to selectthe maximum peak voltage across his current sense resistor. Its powerdissipation can thus be application optimized.

Finally, the bulk input ripple ensures a natural frequency smearingwhich smooths the EMI signature.

Features

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MARKING DIAGRAM

881

SOIC−8D SUFFIXCASE 751

1xAYWWG

1351xAYWWG= A, B, C, or D Options= Assembly Location= Year

= Work Week

= Pb−Free Device

PIN CONNECTIONS

FB1Ct2CS3GND4(Top View)

8TIMER7LATCH6VCC5DRV

ORDERING INFORMATION

DeviceNCP1351ADR2GNCP1351BDR2G

Package

Shipping†

••••••••••••

Quasi−fixed TON, Variable TOFF Current Mode ControlExtremely Low Current Consumption at Startup

Peak Current Compression Reduces Transformer NoisePrimary or Secondary Side RegulationDedicated Latch Input for OTP, OVP

Programmable Current Sense Resistor Peak Voltage

Natural Frequency Dithering for Improved EMI SignatureEasy External Over Power Protection (OPP)Undervoltage Lockout

Very Low Standby Power via Off−time ExpansionInternal Temperature ShutdownSOIC−8 Package

SOIC−82500 / Tape & Reel(Pb−Free)

†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationsBrochure, BRD8011/D.

Typical Applications

•Auxiliary Power Supply

•Printer, Game Stations, Low−Cost Adapters•Off−line Battery Charger

This document contains information on a product under development. ON Semiconductorreserves the right to change or discontinue this product without notice.

November, 2006 − Rev. P2

Publication Order Number:

NCP1351/D

NCP1351

+VOUTNCP1351+85−265VAC*OPPLATCH12348765+GND*OptionalFigure 1. Typical Application Circuit

PIN FUNCTION DESCRIPTION

Pin N°12345678

Pin Name

FBCtCSGNDDRVVCCLatchTimer

FunctionFeedback InputOscillator FrequencyCurrent Sense Input

–Driver OutputSupply InputLatchoff InputFault Timer Capacitor

Pin Description

Injecting Current in this Pin Reduces Frequency

A capacitor sets the maximum switching frequency at no feedback current

Senses the Primary Current

–

Driving Pulses to the Power MOSFETSupplies the controller up to 28 V

A positive voltage above VLATCH fully latches off the controller

Sets the time duration before fault validation

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NCP1351

INTERNAL CIRCUIT ARCHITECTURE

VDD20 ms FilterVTIMERFB

TIMERUVLO ResetFault = Low++−VFaultVDDIP Flag20 ms FilterICtCt

SQQUVLO Reset45kRVDDVCCMngtVZENERVCCSTOP1 = OK0 = not OKClamp4V ResetVDDVOFFset+1 msPulseICS−dif*SICS−dif*QCS

ICS−min*RQGND

Vth+−+*(ICS−diff = ICS−max −ICS−min)Figure 2. A Version (Latched Short−Circuit Protection)

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−++VDDITIMER−++VLATCHLATCHVCC

+−DRVNCP1351

VDDSQVITIMERFB

QUVLO ResetRFault = Low++−VFaultVDDIP Flag20 ms FilterICtCt

SQQUVLO Reset45kRVDDVCCMngtVZENERVCCSTOP1 = OK0 = not OKClamp4V ResetVDDVOFFset+1 msPulseICS−dif*SICS−dif*QCS

ICS−min*RQGND

Vth+−+*(ICS−diff = ICS−max −ICS−min)Figure 3. B Version (Auto−recovery Short−Circuit Protection)

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−++VDDITIMERTIMER−++VLATCHLATCHVCC

+−DRVNCP1351

MAXIMUM RATINGS

SymbolVSUPPLYISUPPLYVDRVIDRVVMAXIMAXIFBmaxRGminRqJATJMAX

Maximum Supply on VCC Pin 6Maximum Current in VCC Pin 6Maximum Voltage on DRV Pin 5Maximum Current in DRV Pin 5

Supply Voltage on all pins, except Pin 6 (VCC), Pin 5 (DRV)Maximum Current in all Pins Except Pin 6 (VCC) and Pin 5 (DRV)Maximum Injected Current in Pin 1 (FB)Minimum Resistive Load on DRV PinThermal Resistance Junction−to−AirMaximum Junction TemperatureStorage Temperature Range

ESD Capability, Human Body Model V per Mil−STD−883, Method 3015ESD Capability, Machine Model

Rating

Value−0.3 to 28

20−0.3 to 20$400−0.3 to 10$100.533200150−60 to +150

2200

UnitVmAVmAVmAmAkW°C/W°C°CkVV

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.

NOTE:This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.

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NCP1351

Electrical Characteristics (For typical values TJ = 25°C, for Min/Max Values TJ = −25°C to +125°C, Max TJ = 150°C, VCC = 12 V

unless otherwise noted)Symbol

SUPPLY SECTION AND VCC MANAGEMENTVCCONVCCSTOPVCCHYSTVZENERICC1ICC2ICC3ICCLATCH

VCC Increasing Level at Which Driving Pulses are AuthorizedVCC Decreasing Level at Which Driving Pulses are StoppedHysteresis VccON − VccSTOP

Clamped VCC When Latched off / Burst Mode ActivationStartup Current

Internal IC Consumption with IFB = 50 mA, FSW = 65 kHz and CL = 0Internal IC Consumption with IFB = 50 mA, FSW = 65 kHz and CL = 1 nFCurrent Flowing into VCC pin that Keeps the Controller Latched

66666666

158.36−−−−20

188.9−6−1.01.6−

229.5−−101.82.5−

VVVVmAmAmAmA

Rating

Min

Typ

Max

Unit

CURRENT SENSEICSminICSminICSmaxICSmaxVTHtdelay

Minimum Source Current (IFB = 90 mA)Minimum Source Current (IFB = 90 mA)Maximum Source Current (IFB = 50 mA)Maximum Source Current (IFB = 50 mA)Current Sense Comparator Threshold Voltage

Propagation Time Delay (CS Falling Edge to Gate Output)

TJ = 0°C to +125°CTJ = −25°C to +125°CTJ = 0°C to +125°CTJ = −25°C to +125°C

333333

615825124210−

707027027020160

75752235300

mAmAmAmAmVns

TIMING CAPACITORVOFFSETVCTMAXICTVCTMINTDISCHVFAULT

Minimum Voltage on CT Capacitor, IFB = 30 mAVoltage on CT Capacitor at IFB = 150 mASource Current (Ct Pin Grounded)

Minimum Voltage on CT, Discharge Switch ActivatedCT Capacitor Discharge Time (Activated at DRV Turn−on)CT Capacitor Level at Which Fault Timer Starts

A, B Versions

222222

0.4475510−

510−11−10.5

0.6565−1220

mVVmAmVmsV

FEEDBACK SECTION

VFBIFAULTIFBcompIFBred

FB Pin Voltage for an Injected Current of 200 mAFB Current Under Which a Fault is DetectedFB Current at Which CS Compression StartsFB Current at Which CS Compression is Finished

A, B versions

1111

−−−−

0.7406080

−−−−

VmAmAmA

Drive Output

TrTfROHROLVDRVlowVDRVhighProtectionITIMERVTIMERTTIMERVLATCH

Timing Capacitor Charging CurrentFault Voltage on Pin 8

Fault Timer Duration, CTIMER = 100 nFLatching Voltage

88−7

104.5−4.5

11.525

135.5−5.5

mAVmsV

Output Voltage Rise−time @ CL = 1 nF, 10 − 90% of Output SignalOutput Voltage Fall−time @ CL = 1 nF, 10 − 90% of Output SignalSource ResistanceSink Resistance

DRV Pin Level at VCC Close to VCCSTOP with a 33 kW Resistor to GNDDRV Pin Level at VCC = 28 V

555555

−−−−8.016

901008030−17

−−−−−20

nsnsWWVV

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NCP1351

The NCP1351 implements a fixed peak current modetechnique whose regulation scheme implements a variableswitching frequency. As shown on the typical applicationdiagram, the controller is designed to operate with aminimum number of external components. It incorporatesthe following features:

•Frequency Foldback: Since the switching period

increases when power demand decreases, the switchingfrequency naturally diminishes in light load conditions.This helps to minimize switching losses and offersgood standby power performance.

•Very Low Startup Current: The patented internalsupply block is specially designed to offer a very lowcurrent consumption during startup. It allows the use ofa very high value external startup resistor, greatlyreducing dissipation, improving efficiency andminimizing standby power consumption.

•Natural Frequency Dithering: The quasi−fixed tONmode of operation improves the EMI signature sincethe switching frequency varies with the natural bulkripple voltage.

•Peak Current Compression: As the load becomeslighter, the frequency decreases and can enter theaudible range. To avoid exciting transformer

mechanical resonances, hence generating acousticnoise, the NCP1351 includes a patented technique,

which reduces the peak current as power goes down. Assuch, inexpensive transformer can be used withouthaving noise problems.

•Negative Primary Current Sensing: By sensing thetotal current, this technique does not modify theMOSFET driving voltage (VGS) while switching.Furthermore, the programming resistor, together with

the pin capacitance, forms a residual noise filter whichblanks spurious spikes.

Programmable Primary Current Sense: It offers asecond peak current adjustment variable, whichimproves the design flexibility.

Extended VCC Range: By accepting VCC levels up to28 V, the device offers added flexibility in presence ofloosely coupled transformers. The gate drive is safelyclamped below 20 V to avoid stressing the drivenMOSFET.

Easy OPP: Connecting a resistor from the CS pin tothe auxiliary winding allows easy bulk voltagecompensation.

Secondary or Primary Regulation: The feedbackloop arrangement allows simple secondary or primaryside regulation without significant additional externalcomponents.

Latch Input: If voltage on Pin 7 is externally broughtabove 5 V, the controller permanently latches off andstays latched until the user cycles VCC down, below 4V typically.

Fault Timer: In presence of badly coupled transformer,it can be quite difficult to detect an overload or ashort−circuit on the primary side. When the feedbackcurrent disappears, a current source charges a capacitorconnected to Pin 8. When the voltage on this pinreaches a certain level, all pulses are shut off and theVCC voltage is pulled down below the VCC(min) level.This protection is latched on the A version (thecontroller must be shut down and restart to resumenormal operation), and auto−recovery on Version B (ifthe fault goes away, the controller automaticallyresumes operation).

••

•

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NCP1351

APPLICATION INFORMATION

The Negative Sensing Technique

Standard current−mode controllers use the positivesensing technique as portrayed by Figure 4. In thistechnique, the controller detects a positive voltage dropacross the sense resistor, representative of the flowingcurrent. Unfortunately, this solution suffers from thefollowing drawbacks:

1.Difficulties to precisely adjust the peak current. If1 V is the maximum sense level, you must

combine low valued resistors to reach the exactlimit you need.

2.The voltage developed across the sense resistorsubtracts from the gate voltage. If your VCC(min)is 7 V, then the actual gate voltage at the end of theon time, assuming a full load condition, is 7 V –1 V = 6 V.

3.The current in the sense resistor also includes theCiss current at turn−on. This narrow spike oftendisturbs the controller and requires adequatetreatment through a LEB circuitry for instance.Figure 5 represents the negative current sense technique.In this simplified example, the source directly connects tothe controller ground. Hence, if VCC is 8 V, the effectivegate−source voltage is very close to 8 V: no sense resistordrop. How does the controller detect a negative excursion?In lack of primary current, the voltage on the CS pin reachesRoffset x ICS. Let us assume that these elements lead to have1 V on this pin. Now, when the power MOSFET activates,the current flows via the sense resistor and develop anegative voltage by respect to the controller ground. Thevoltage seen on the CS is nothing else than a positive voltage(Roffset x ICS) plus the voltage across the sense resistor whichis negative. Thus, the CS pin voltage goes low as the primary

ILpcurrent increases. When the result reaches the thresholdvoltage (around 20 mV), the comparator toggles and resetsthe main latch. Figure 3 details how the voltage moves on theCS pin on a 1351 demoboard, whereas Figure 7 zooms onthe sense resistor voltage captured by respect to thecontroller ground.

The choice of these two elements is simple. Suppose youwant to develop 1 V across the sense resistor. You wouldselect the offset resistor via the following formula:

Roffset+

1ICS

+3.7kW270m

(eq. 1)

If you need a peak current of 2 A, then, simply apply theohm law to obtain the sense resistor value:

Rsense+

1Ipeak_max

+0.5W2

(eq. 2)

Due to the circuit flexibility, suppose you only have accessto a 0.33 W resistor. In that case, the peak current will exceedthe 2 A limit. Why not changing the offset resistor valuethen? To obtain 2 A from the 0.33 W resistor, you shoulddevelop:

The offset resistor is thus derived by:

Vsense+RsenseIpeak_max+0.33 2+660mV

(eq. 3)

Roffset+

0.66ICS

0.66

+2.44kW270m

(eq. 4)

If reducing the sense resistor is of good practice toimprove the efficiency, we recommend to adopt sense valuesbetween 0.5 V and 1 V. Reducing the voltage below theselevels will degrade the noise immunity.

LPLPDRV++DRVVDDCSICS−CBulkCSILpReset+−VgsILpCBulkILpResetGNDILpPeakSetpointRsenseGNDILpVsenseVoffsetRoffset++VthILpVsense

Figure 4. Positive Current−Sense Technique

Figure 5. A Simplified Circuit of the Negative Sense

Implementation

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NCP1351

Current Sense Resistor

Current Sense Pin

Figure 6. The Voltage on the Current Sense Pin

Figure 7. The Voltage Across the Sense

Resistor

Below are a few recommendations concerning the wiringand the PCB layout:

•A small 22 pF capacitor can be placed between the CSpin and the controller ground. Place it as close aspossible to the controller.

•Do not place the offset resistor in the vicinity of thesense element, but put it close to the controller as well.•Regulation by frequency

•The power a flyback converter can deliver relates to theenergy stored in the primary inductance Lp and obeysthe following formulae:

Pout_DCM+

LPIpeak2FSWh2

(eq. 5)(eq. 6)

Pout_CCM+12LP(Ipeak2*Ivalley2)FSWh

Where:

η (eta) is the converter efficiency

Ipeak is the peak inductor current reached at the on timetermination

Ivalley represents the current at the end of the off time. Itequals zero in DCM.

FSW is the operating frequency.

VCtThus, to control the delivered power, we can either play onthe peak current setpoint (classical peak current modecontrol) or adjust the switching frequency by keeping thepeak current constant. We have chosen the second schemein this NCP1351 for simplicity and ease of implementation.Thus, once the peak current has been selected, the feedbackloop automatically reacts to satisfy Equations 5 and 6. Theexternal capacitor that you connect between pin 2 andground (again, place it close to the controller pins) sets themaximum frequency you authorize the converter to operateup to. Normalized values for this timing capacitor are270 pF (65 kHz) and 180 pF (100 kHz). Of course, differentcombinations can be tried to design at higher or lowerfrequencies. Please note that changing the capacitor valuedoes not affect the operating frequency at nominal line andload conditions. Again, the operating frequency is selectedby the feedback loop to cope with Equations 5 and 6definitions.

The feedback current controls the frequency by changingthe timing capacitor end of charge voltage, as illustrated byFigure 8.

Controlled by theFB CurrentMinimum FrequencyPout

DecreasesPout

Increases

ICt = 10 mAMaximum FrequencyFigure 8. The Current Injected into the Feedback Loop Adjusts the Switching Frequency

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NCP1351

Ct Voltage

Figure 9. In Light Load Conditions, theOscillator Further Delays the Restart TimeFigure 10. Ct Voltage Swing at a Moderate

In light load conditions, the frequency can go down to afew hundred Hz without any problem. The internal circuitrynaturally blocks the oscillator and softly shifts the restarttime as shown on Figure 9 scope shot.

Delays The Restart Time

D11N4148DRV

Q12N2907GND

In lack of feedback current, for instance during a startupsequence or a short circuit, the oscillator frequency is pushedto the limit set by the timing capacitor. In this case, the lowerthreshold imposed to the timing capacitor is blocked to500 mV (parameter Vfault). This is the maximum power theconverter can deliver. To the opposite, as you inject currentvia the optocoupler in the feedback pin, the off time expandsand the power delivery reduces. The maximum thresholdlevel in standby conditions is set to 6 V.

Over Power Protection

Figure 11. A Low−Cost PNP Improves the Drive

Capability at Turn−off

As any universal−mains operated converters, the outputpower slightly increases at high line compared to what thepower supply can deliver at low line. This discrepancyrelates to the propagation delay from the point where thepeak is detected to the MOSFET gate effective pulldown. Itnaturally includes the controller reaction time, but also thedriver capability to pull the gate down. If the MOSFET Qgis too large, then this parameter will greatly affect youroverpower parameter. Sometimes, the small PNP can helpand we recommend it if you use a large Qg MOSFET:

Over power protection can be done without powerdissipation penalty by arranging components around theauxiliary as suggested by Figure 11. On this schematic, thediode anode swings negative during the on time. Thisnegative level directly depends on the input voltage andoffsets the current sense pin via the ROPP resistor. A smallintegration is necessary to reduce the OPP action in light loadconditions. However, depending on the compensation level,the standby power can be affected. Again, the resistor ROPPshould be placed as close as possible to the CS pin. The22 pF can help to circumvent any picked−up noise and D2prevents the positive loading of the 270 pF capacitor duringthe flyback swing. We have put a typical 100 kW OPPresistor but a tweak is required depending on yourapplication.

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NCP1351

LPDRV+DRVDaux+CSC422pCBulkVCCILpCVCCLauxR1150kC3270pRoffsetRsenseD21N4148ROPP100k

Figure 12. The OPP is Relatively Easy to Implement and It Does not Waste Power

Suppose you would need to reduce the peak current by15% in high−line conditions. The turn−ratio between theauxiliary winding and the primary winding is Naux. Assumeits value is 0.15. Thus, the voltage on Daux cathode swingsnegative during the on time to a level of:

Vaux_peak+−Vin_maxNaux+−375 0.15+−56V

(eq. 7)

15%. Compared to the internal 270 mA source, we need toderive:

Ioffset+−0.15 270m+−40.5mA

(eq. 10)

Thus, from the –4 V excursion, the ROPP resistor isderived by:

ROPP+

+98kW

40.5m

(eq. 11)

If we selected a 3.7 kW resistor for Roffset, then themaximum sense voltage being developed is:

Vsense+3.7k 270m+1V

(eq. 8)

After experimental measurements, the resistor wasnormalized down to 100 kW.

Feedback

The small RC network made of R1 and C3, purposely limitsthe voltage excursion on D2 anode. Assume the primaryinductance value gives an on time of 3 μs at high−line. Thevoltage across C3 thus swings down to:

VC3+

tonVaux_peak

R1C3

+−

3m 56150k 270p

+−4.2V

(eq. 9)

Unlike other controllers, the feedback in the NCP1351works in current rather than voltage. Figure 13 details theinternal circuitry of this particular section. The optocouplerinjects a current into the FB pin in relationship with theinput/output conditions.

Typically, we measured around –4 V on our 50 W prototype.By calculation, we want to decrease the peak current by

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NCP1351

VCC

ICt10mCtCt270pVCCResetFBIFBIFBVoffset500mV+−+Clock

C1100nR12.5kDFBIFBRFB45kVCC

C322pFCSICSminIdiffIdiffIdiff = ICSmax − ICSminRoffset3.9kf(IFB)

to Rsense

Figure 13. The Feedback Section Inside the NCP1351

The FB pin can actually be seen as a diode, forward biasedby the optocoupler current. The feedback current, IFB onFigure 13, enter an internal 45 kW resistor which developsa voltage. This voltage becomes the variable threshold pointfor the capacitor charge, as indicated by Figure 8. Thus, inlack of feedback current (start−up or short−circuit), there isno voltage across the 45 kW and the series offset of 500 mVclamps the capacitor swing. If a 270 pF capacitor is used, themaximum switching frequency is 65 kHz.

Folding the frequency back at a rather high peak currentcan obviously generate audible noise. For this reason, theNCP1351 uses a patented current compression techniquewhich reduces the peak current in lighter load conditions. Bydesign, the peak current changes from 100% of its full loadvalue, to 30% of this value in light load conditions. This isthe block placed on the lower left corner of Figure 13. In full

load conditions, the feedback current is weak and all thecurrent flowing through the external offset resistor is:

ICS+ICS_min)Idif+ICS_max*ICS_min

+ICS_max

(eq. 12)

As the load goes lighter, the feedback current increases andstarts to steal current away from the generators. Equation 12can thus be updated by:

ICS+ICS_max*kIFB

(eq. 13)

Equation 13 testifies for the current reduction on the offsetgenerator, k represents an internal coefficient. When thefeedback current equals Idif, the offset becomes:

ICS+ICS_min

(eq. 14)

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NCP1351

At this point, the current is fully compressed and remainsfrozen. To further decrease the transmitted power, thefrequency does not have other choice than going down.

CS Current250 mAR12.5kFAULT(A, B versions)C1100nFVCC

FB70 mAFigure 15. The Recommended Feedback

Arrangement Around the FB Pin

40 mA60 mA80 mAFault detection

FB CurrentFigure 14. The NCP1351 Peak Current Compression

Scheme

Looking to the data−sheet specifications, the maximumpeak current is set to 270 mA whereas the compressedcurrent goes down to 70 mA. The NCP1351 can thus beconsidered as a multi operating mode circuit:

•Real fixed peak current / variable frequency mode forFB current below 60 mA.

•Then maximum peak current decreases to ICS,min over anarrow linear range of IFB (to avoid instability createdby a discrete jump from ICS,max to ICS,min), between60 mA and 80 mA.

•Then if IFB keeps on increasing, in a real fixed peakcurrent/variable frequency mode with reduced peakcurrent

For biasing purposes and noise immunity improvements,we recommend to wire a pulldown resistor and a capacitorin parallel from the FB pin to the controller ground(Figure 15). Please keep these elements as close as possibleto the circuit. The pulldown resistor increases theoptocoupler current but also plays a role in standby. Wefound that a 2.5 kW resistor was giving a good tradeoffbetween optocoupler operating current (internal poleposition) and standby power.

The fault detection circuitry permanently observes the FBcurrent, as shown on Figure 17. When the feedback currentdecreases below 40 mA, an external capacitor is charged bya 11.7 mA source. As the voltage rises, a comparator detectswhen it reaches 5 V typical. Upon detection, there can betwo different scenarios:

1.A version: the circuit immediately latches−off andremains latched until the voltage on the currentinto the VCC pin drops below a few μA. The latchis made via an internal SCR circuit who holds Vccto around 6 V when fired. As long as the currentflowing through this latch is above a few mA, thecircuit remains locked−out. When the user unplugsthe converter, the VCC current falls down andresets the latch.

2.B version: the circuit stops its output pulses andthe auxiliary VCC decreases via the controller ownconsumption (≈600 mA). When it touches the

VCC(min) point, the circuit re−starts and attempts tocrank the power supply. If it fails again, an hiccupmode takes place (Figure 13).

VCC

Vdrv

Figure 16. Hiccup Occurs with the B Version Only,

the A Version Being Latched

The duty−burst in fault is around 7% in this particularcase.

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NCP1351

VCCItimer10mTimerCtimer100nFVCCPonResetIFBDFB+VCC+−SQQRIFBIFB+Daux+20msFilterICCCVCCLauxVtimer5to DRVStageFBC1100nR12.5k−+VCC ==VCC(min) ? ResetDRV PulsesIFB < 40 mA ? = LowElse = HighVCCItimer10mTimerCtimer100nFVCCPonResetIFBDFBAuto−Recovery − B VersionVCC+−20msFilter6VCVCC+DauxLauxICC+Vtimer5FBC1100nR12.5kIFBIFB+−+SCR Delatches WhenISCR < ICClatch (Few mA)IFB < 40 mA ? = LowElse = HighLatched − A VersionFigure 17. The Internal Fault Management Differs Depending on the Considered Version

Knowing both the ending voltage and the charge current,we can easily calculate the timer capacitor value for a givendelay. Suppose we need 40 ms. In that case, the capacitor issimply:

11.7m 40mIT

Ctimer+timer++94nF

5Vtimer

(eq. 15)

the target). Yes, you can use this reference voltage to supply

a NTC and form a cheap OTP protection.

VCC

Select a 100 nF value.

Latch Input

5VC2100nR12.5kFBLatchOVPD2The NCP1351 features a patented circuitry whichprevents the FB input to be of low impedance before the Vccreaches the VCCON level. As such, the circuit can work ina primary regulation scheme. Capitalizing on this typicaloption, Figure 18 shows how to insert a zener diode in serieswith the optocoupler emitter pin. In that way, the currentbiases the zener diode and offers a nice reference voltage,appearing at the loop closure (e.g. when the output reaches

C1100nFRpulldownC3100nFFigure 18. The Latch Input Offers Everything Neededto Implement an OTP Circuit. Another Zener CanHelp combining an OVP Circuit if Necessary

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NCP1351

VCCVCCAux+OUT

+CVCC20mFLauxR42.2kCVCC22mFSecU1AU1BLatchRpulldownROVPC3100nFD21N4937C4100nC51nLatchC1100nFD4Figure 19. You can either directly observe the VCC level or add a small RC filter to reduce the leakage inductancecontribution. The best is to directly sense the output voltage and reacts if it runs away, as offered on the right

side.Design Example, a 19 V / 3

Solving for N gives:

kCǒVout)VfǓ1.6 (19)0.8)Ns

N+++

Np135Vclamp+0.234

(eq. 19)

A Universal Mains Power Supply Designing a

Switch−Mode Power Supply using the NCP1351 does notdiffer from a fixed frequency design. What changes,however, is the regulation method via frequency variations.In other words, all the calculations must be carried at thelowest line input where the frequency will hit the maximumvalue set by the Ct capacitor. Let us follow the steps:Vin min = 100 Vdc (bulk valley in low−line conditions)Vin max = 375 VdcVout = 19 VIout = 3 A

Operating mode is CCMη = 0.8

Fsw = 65 kHz

1.Turn Ratio. This is the first parameter to consider.The MOSFET BVdss actually dictates the amountof reflected voltage you need. If we consider a600 V MOSFET and a 15% derating factor, wemust limit the maximum drain voltage to:

Vds_max+600 0.85+510V

(eq. 16)

Let us round it to 0.25 or 1/N = 4

IpeakI1IvalleyDIL

IavgKnowing a maximum bulk voltage of 375 V, the clampvoltage must be set to:

Vclamp+510*375+135V

(eq. 17)

DTSWTSW

Based on the above level, we decide to adopt a headroombetween the reflected voltage and the clamp level of 50 V. Ifthis headroom is too small, a high dissipation will occur onthe RDC clamp network and efficiency will suffer. Aleakage inductance of around 1% of the magnetizing valueshould give good results with this choice (kc = 1.6). The turnratio between primary and secondary is simply:

ǒVout)VfǓ

+Vclampkc

(eq. 18)

Figure 20. Primary Inductance Current Evolution

in CCM

2.Calculate the maximum operating duty−cycle forthis flyback converter operated in CCM:

dmax+

VoutńNVoutńN)Vin_min

19 4

+0.43

19 4)100

(eq. 20)

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NCP1351

In this equation, the CCM duty−cycle does not exceed50%. The design should thus be free of subharmonicoscillations in steady−state conditions. If necessary,negative ramp compensation is however feasible by theauxiliary winding.

3.To obtain the primary inductance, we can use thefollowing equation which expresses the inductancein relationship to a coefficient k. This coefficientactually dictates the depth of the CCM operation.If it goes to 2, then we are in DCM.

L+

(Vin_mindmax)2

FSWKPin

(eq. 21)

On Figure 20, I1 can also be calculated:

II+Ipeak*

1.34DIL

+2.33*+1.65A

(eq. 26)

The valley current is also found to be:

Ivalley+Ipeak*DIL+2.33*u1.34+1.0A(eq. 27)

4.Based on the above numbers, we can now evaluate

the RMS current circulating in the MOSFET andthe sense resistor:

Id_rms+IIǸd

where K = DIL/II and defines the amount of ripple we wantin CCM (see Figure 20).

•Small K: deep CCM, implying a large primaryinductance, a low bandwidth and a large leakageinductance.

•Large K: approaching BCM where the RMS losses arethe worse, but smaller inductance, leading to a betterleakage inductance.From Equation 16, a K factor of 0.8 (40% ripple) ensures agood operation over universal mains. It leads to aninductance of:

L+

(100 43)265k 0.8 72

+493mH

(eq. 22)

Ǹ1)1ǒDILǓ2

32I1

+1.65 0.65 Ǹ1)1ǒ+1.1A

1.34232 1.65

Ǔ(eq. 28)

5.The current peaks to 2.33 A. Selecting a 1 V dropacross the sense resistor, we can compute its value:

Rsense+

1Ipeak

+0.4W2.5

(eq. 29)

To generate 1 V, the offset resistor will be 3.7 kW, as alreadyexplained. Using Equation 28, the power dissipated in thesense element reaches:

Psense+RsenseId_rms2+0.4 1.12+484mW

(eq. 30)

DIL+

Vin_mindmax19 3

0.8 100LFSW

(eq. 23)

+1.34Apeak−to−peak

The peak current can be evaluated to be:

Iin_avg+

Pout100 0.43++712mA(eq. 24)

V493m 65khin_mind)

0.7121.34DIL

+)+2.33A

0.4322

(eq. 25)

6.To switch at 65 kHz, the Ct capacitor connected to

pin 2 will be selected to 180 pF.

7.As the load changes, the operating frequency willautomatically adjust to satisfy either equation 5(high power, CCM) or equation 6 in lighter loadconditions (DCM).Figure 21 portrays a possible application schematicimplementing what we discussed in the above lines.

Ipeak+

Iavg

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NCP1351

HV−BulkR71MR21MD2MUR1608765NCP1351BR1610R1847kC4100nR52.5kC9100nC8270pFR12.2kC100.1m++C17100mR910kOVPOptionD61N4148D31N4937R347k

R1347kR422C210n400VLP = 500mHNP:NS = 1:0.25NP:Naux = 0.18D5MBR20200C5a1.2mF25VC132.2nFType = Y1T1+C5b1.2mF25V+L22.2mC7220mF25V+VOUT 19V/3AU1B1C12+100mF400VR153.7kC1522p234U2R81kGNDR124kR1062k25V6A/600VM1U1AR142.2kC6100nIC2TL431R60.4C3C14.7m100nF25V

GNDFigure 21. The 19 V Adapter Featuring the Elements Calculated Above

On this circuit, the VCC capacitor is split in two parts, alow value capacitor (4.7 mF) and a bigger one (100 mF). The4.7 mF capacitor ensures a low startup time, whereas thesecond capacitor keeps the VCC alive in standby mode(where the switching frequency can be low). Due to D6, itdoes not hamper startup time.

Application Results

Another benefit of the variable frequency lies in the lowripple operation at no−load. This is what confirmsFigure 23.

Finally, the power supply was tested for its transientresponse, from 100 mA to 3 A, high and low line, with aslew−rate of 1 A/ms (Figure 25). Results appear inFigures 25 and 26 and confirm the stability of the board.

We assembled a board with component values close towhat is described on Figure 21. Here are the obtainedresults:

Pin @ no−load = 152 mW, Vin = 230 VacPin @ no−load = 1 mW, Vin = 100 Vac

The efficiency stays flat to above 80%, and keeps goodeven at low output levels. It clearly shows the benefit of thevariable frequency implemented in the NCP1351.

888684EFFICIENCY (%)8280787674720

0.5

1.52Iout (A)

2.5

3.5

Vin = 100 VacVin = 230 VacFigure 22. Efficiency Measured at Various Operating

Points

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NCP1351

Vds200 V/divVds200 V/div

Vout1.0 mV/div

Figure 23. No−Load Output Ripple

(Vin = 230 Vac)Figure 24. Same Conditions,

Pout = 5 W

Vout50 mV/div

Figure 25. Transient Step, Low LineFigure 26. Transient Step, High Line

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NCP1351

PACKAGE DIMENSIONS

SOIC−8D SUFFIXCASE 751−07ISSUE AH

−X−A85NOTES:

1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.

2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A AND B DO NOT INCLUDEMOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.

5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6.751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

MILLIMETERSMINMAX4.805.003.804.001.351.750.330.511.27 BSC0.100.250.190.250.401.270 _8 _0.250.505.806.20

INCHES

MINMAX0.10.1970.1500.1570.0530.0690.0130.0200.050 BSC0.0040.0100.0070.0100.0160.0500 _8 _0.0100.0200.2280.244

B1S40.25 (0.010)MYM−Y−GKC−Z−HD0.25 (0.010)

MSEATINGPLANENX 45_0.10 (0.004)MJZY

SDIMABCDGHJKMNS

SOLDERING FOOTPRINT*

1.520.0607.00.27.00.1550.60.0241.2700.050SCALE 6:1

mmǓǒinches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 303−675−2175 or 800−344−3860 Toll Free USA/CanadaFax: 303−675−2176 or 800−344−3867 Toll Free USA/CanadaEmail: orderlit@onsemi.comN. American Technical Support: 800−282−9855 Toll FreeUSA/CanadaEurope, Middle East and Africa Technical Support:Phone: 421 33 790 2910Japan Customer Focus CenterPhone: 81−3−5773−3850ON Semiconductor Website: www.onsemi.comOrder Literature: http://www.onsemi.com/orderlitFor additional information, please contact your localSales Representativehttp://onsemi.com19NCP1351/D

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